Method of forming an electrical connection to an electronic module
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H05K-003/30
H05K-001/14
H05K-001/18
H05K-001/02
H05K-003/36
B23K-001/00
B23K-001/20
출원번호
US-0596914
(2015-01-14)
등록번호
US-9936580
(2018-04-03)
발명자
/ 주소
Vinciarelli, Patrizio
Balcius, Robert Joseph
Sadler, Steven P.
Thompson, Mark Andrew
출원인 / 주소
VLT, Inc.
대리인 / 주소
Fish & Richardson P.C.
인용정보
피인용 횟수 :
1인용 특허 :
26
초록▼
Circuit assemblies can be electrically interconnected by providing a circuit assembly having a top surface, a bottom surface, and a perimeter edge connecting the top and bottom surfaces, the perimeter edge being formed of insulative material and having a plurality of conductive features embedded in
Circuit assemblies can be electrically interconnected by providing a circuit assembly having a top surface, a bottom surface, and a perimeter edge connecting the top and bottom surfaces, the perimeter edge being formed of insulative material and having a plurality of conductive features embedded in and exposed on the surface of the edge. The conductive features are arranged in contact sets, and each contact set is separated from adjacent contact sets by a portion of the perimeter edge that is free of conductive features. Each contact set includes conductive features that together form a distributed electrical connection to a single node. The insulative material is selectively removed to form recesses adjacent the conductive features exposing additional surface contact areas along lateral portions of the conductive features in the recesses.
대표청구항▼
1. A method of forming an electrical connection to an electronic module, the method comprising: assembling a panel including a substrate and having one or more conductive features enclosed within the panel and unexposed to an exterior surface of the panel, the one or more conductive features each be
1. A method of forming an electrical connection to an electronic module, the method comprising: assembling a panel including a substrate and having one or more conductive features enclosed within the panel and unexposed to an exterior surface of the panel, the one or more conductive features each being electrically connected to a respective electrical node of the panel and being located along a cut line;cutting the panel along the cut line exposing a contact edge of each of the one or more conductive features, wherein each contact edge is embedded in and forms part of a perimeter surface of the electronic module after the cutting; andselectively removing portions of material from the perimeter surface adjacent to selected ones of the contact edges of selected ones of the conductive features exposing additional portions of the selected ones of the conductive features,wherein the additional portions are recessed from the perimeter edge and together with the adjacent exposed edge forms a three dimensional contact. 2. The method of claim 1 further comprising preparing the contact edges and the additional portions of the conductive feature for solder wetting. 3. The method of claim 1 further comprising wetting the contact edges and the additional portions of the conductive features with solder. 4. The method of claim 1 further comprising forming a metallic bond between the contact edges and the additional portions and an external conductive terminal. 5. The method of claim 4, further comprising encapsulating the panel prior to cutting the panel, and cutting the panel comprises cutting the encapsulated panel. 6. The method of claim 1 further comprising forming a metallic bond between the contact edges and the additional portions of the conductive features and a conductive pad on a printed circuit board. 7. The method of claim 6, further comprising encapsulating the panel prior to cutting the panel, and cutting the panel comprises cutting the encapsulated panel. 8. The method of claim 1 further comprising forming a solder connection between the contact edges and the additional portions of the conductive features and a terminal of a lead frame. 9. The method of claim 8, further comprising encapsulating the panel prior to cutting the panel, and cutting the panel comprises cutting the encapsulated panel. 10. The method of claim 1 wherein the additional portions have surface areas that form angles greater than 45 degrees to the perimeter edge. 11. The method of claim 1, comprising forming a plurality of three dimensional contacts, arranging the three dimensional contacts in a plurality of contact sets, each contact set having a plurality of three dimensional contacts, in which each contact set is separated from adjacent contact sets by a portion of the perimeter edge that is free of conductive features, andusing the plurality of three dimensional contacts of each contact set together to form a distributed electrical connection to a single electrical node in the circuit assembly. 12. The method of claim 11 in which each contact set is separated from adjacent contact sets by a portion of the perimeter edge that is free of conductive features, in which a first distance between two adjacent contact sets is at least twice as large as a second distance between two adjacent conductive features, the first and second distances being measured along a direction substantially perpendicular to a top surface. 13. The method of claim 11 in which each contact set is separated from adjacent contact sets by a portion of the perimeter edge that is free of conductive features, in which a first distance between two adjacent contact sets is at least five times as large as a second distance between two adjacent conductive features, the first and second distances being measured along a direction substantially perpendicular to a top surface. 14. The method of claim 11, further comprising electrically coupling an external conductive terminal to a selected contact set. 15. The method of claim 11, further comprising solder connecting each conductive pad of an external circuit board to a respective contact set. 16. The method of claim 11, further comprising solder connecting each terminal of a lead frame to a respective contact set. 17. The method of claim 11, further comprising encapsulating the panel prior to cutting the panel, and cutting the panel comprises cutting the encapsulated panel. 18. The method of claim 1 wherein assembling a panel including a substrate comprises assembling a panel including a printed circuit board (“PCB”), cutting the panel along the cut line exposing a contact edge comprises cutting the PCB exposing a contact edge of the PCB, the PCB has a plurality of conductive layers, and the conductive features comprise selected portions of the conductive layers and are located at an elevation in the perimeter surface between a first surface and a second surface. 19. The method of claim 18 wherein selectively removing portions of material from the perimeter surface comprises selectively removing portions of the material in insulation layers in the PCB. 20. The method of claim 1, further comprising encapsulating the panel prior to cutting the panel, and cutting the panel comprises cutting the encapsulated panel. 21. A method of forming an electrical connection to an electronic module, the method comprising: assembling a panel of electronic circuitry including a printed circuit board (“PCB”), a plurality of electronic components mounted to the PCB, and having one or more conductive features enclosed within the panel and unexposed to an exterior surface of the panel, the one or more conductive features each being electrically connected to a respective electrical node of the panel and being located along a cut line;cutting the assembled panel and the PCB along the cut line exposing a contact edge of the PCB and each of the one or more conductive features, wherein each contact edge is embedded in and forms part of a perimeter surface of the electronic module after the cutting; andselectively removing portions of material from the perimeter surface adjacent to selected ones of the contact edges of selected ones of the conductive features exposing additional portions of the selected ones of the conductive features,wherein the additional portions are recessed from the perimeter edge and together with the adjacent exposed edge forms a three dimensional contact. 22. The method of claim 21, further comprising encapsulating the panel prior to cutting the panel, and cutting the panel comprises cutting the encapsulated panel. 23. The method of claim 21 wherein the PCB has a plurality of conductive layers, the conductive features comprise selected portions of the conductive layers and are located at an elevation in the perimeter surface between a first surface and a second surface, and selectively removing portions of material from the perimeter surface comprises selectively removing portions of the material in insulation layers in the PCB. 24. The method of claim 23, further comprising forming a plurality of three dimensional contacts, arranging the three dimensional contacts in a plurality of contact sets, each contact set having a plurality of three dimensional contacts, in which each contact set is separated from adjacent contact sets by a portion of the perimeter edge that is free of conductive features, andusing the plurality of three dimensional contacts of each contact set together to form a distributed electrical connection to a single electrical node in the circuit assembly. 25. The method of claim 24 further comprising separating each contact set from adjacent contact sets by a portion of the perimeter edge that is free of conductive features, wherein a first distance between two adjacent contact sets is at least twice as large as a second distance between two adjacent conductive features, the first and second distances being measured along a direction substantially perpendicular to a top surface. 26. The method of claim 24 further comprising separating each contact set from adjacent contact sets by a portion of the perimeter edge that is free of conductive features, wherein a first distance between two adjacent contact sets is at least five times as large as a second distance between two adjacent conductive features, the first and second distances being measured along a direction substantially perpendicular to a top surface. 27. The method of claim 24 wherein the selectively removing portions of the material in insulation layers in the PCB further comprises plasma etching the insulation layers in the PCB in an etching region. 28. The method of claim 27 wherein the selectively removing portions of the material in insulation layers in the PCB further comprises masking selected areas outside of the etching region before the plasma etching to protect the selected areas. 29. The method of claim 28 wherein the selectively removing portions of the material in insulation layers in the PCB further comprises media blasting the etching region after the plasma etching the etching region. 30. The method of claim 29 wherein the media blasting comprises using dry ice, CO2 as the blast media. 31. The method of claim 30 further comprising forming a solder connection to at least one contact set including a solder joint between the plurality of three dimensional contacts of each contact set and a respective external conductor. 32. The method of claim 31 wherein the respective external conductor comprises a conductive feature of an external PCB. 33. The method of claim 31 wherein the respective external conductor comprises a conductive lead of an adapter or lead set.
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이 특허에 인용된 특허 (26)
John R. Saxelby, Jr. ; Walter R. Hedlund, III, Circuit encapsulation.
Combs, Edward G.; Sheppard, Robert P.; Pun, Tai Wai; Ng, Hau Wan; Fan, Chun Ho; McLellen, Neil Robert, Enhanced thermal dissipation integrated circuit package.
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