Tristate multiplexers with immunity to aging effects
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H03K-019/003
H03K-019/00
H03K-019/173
출원번호
US-0213031
(2016-07-18)
등록번호
US-9941882
(2018-04-10)
발명자
/ 주소
Lewis, David
출원인 / 주소
Altera Corporation
대리인 / 주소
Treyz Law Group, P.C.
인용정보
피인용 횟수 :
0인용 특허 :
9
초록▼
An integrated circuit with programmable logic is provided. The programmable logic may include multiplexers that are actively used by a custom logic design or unused. To ensure that these multiplexers do not suffer from aging effects when they are not in use, the multiplexers may be provided with agi
An integrated circuit with programmable logic is provided. The programmable logic may include multiplexers that are actively used by a custom logic design or unused. To ensure that these multiplexers do not suffer from aging effects when they are not in use, the multiplexers may be provided with aging prevention circuitry. In particular, such a multiplexer may include an input selection stage that is coupled in series with a tristate buffer stage. The input selection stage may include pass transistors or full CMOS transmission gates. The tristate buffer stage may include at least two pairs of output driving transistors, with gates that are selectively shorted when the multiplexer is activated using additional transmission gate circuits. The aging prevention circuitry may include tie-off transistors that are activated to drive the gate-to-source voltages of the output driving transistors to zero volts whenever the multiplexer is not in use.
대표청구항▼
1. An integrated circuit, comprising: a multiplexing circuit operable in an active mode and a tristate mode, wherein the multiplexing circuit comprises: an input selection stage; anda tristate buffer stage that receives signals from the input selection stage and that includes driving transistors and
1. An integrated circuit, comprising: a multiplexing circuit operable in an active mode and a tristate mode, wherein the multiplexing circuit comprises: an input selection stage; anda tristate buffer stage that receives signals from the input selection stage and that includes driving transistors and aging prevention circuitry, wherein: the aging prevention circuitry nullifies any gate-to-source voltage on the driving transistors;the driving transistors in the tristate buffer stage includes: a first pull-down transistor with a gate terminal connected to the input selection stage, a first pull-up transistor with a gate terminal connected to the input selection stage, a second pull-down transistor with a gate terminal that is connected to the first pull-down transistor, and a second pull-up transistor with a gate terminal that is connected to the first pull-up transistor; andthe aging prevention circuitry in the tristate buffer stage includes: a first tie-off transistor for selectively driving the gate terminal of the first pull-down transistor to a ground power supply voltage level, a second tie-off transistor for selectively driving the gate terminal of the first pull-up transistor to a positive power supply voltage level, a third tie-off transistor for selectively driving the gate terminal of the second pull-down transistor to the ground power supply voltage level, and a fourth tie-off transistor for selectively driving the gate terminal of the second pull-up transistor to the positive power supply voltage level. 2. The integrated circuit of claim 1, wherein the tristate buffer stage further comprises: a transmission gate coupled between the gate terminals of the first pull-down transistor and the first pull-up transistor. 3. The integrated circuit of claim 2, wherein the first and second tie-off transistors and the transmission gate are controlled by an enable signal. 4. The integrated circuit of claim 1, wherein the second pull-down transistor and the second pull-up transistor are directly connected to an output terminal of the multiplexing circuit. 5. The integrated circuit of claim 1, wherein the tristate buffer stage further comprises: a transmission gate coupled between the gate terminals of the second pull-down transistor and the second pull-up transistor. 6. The integrated circuit of claim 1, wherein the input selection stage comprises: a first group of pass transistors of a first channel type connected to the gate terminal of the first pull-up transistor; anda second group of pass transistors of a second channel type connected to the gate terminal of the first pull-down transistor, wherein the first and second channel types are different channel types. 7. The integrated circuit of claim 1, wherein the input selection stage comprises: a first group of transmission gates coupled to the gate terminal of the first pull-up transistor; anda second group of transmission gates coupled to the gate terminal of the first pull-down transistor. 8. An integrated circuit, comprising: a multiplexing circuit operable in an active mode and a tristate mode, wherein the multiplexing circuit comprises: an input selection stage; anda tristate buffer stage that receives signals from the input selection stage and that includes driving transistors and aging prevention circuitry, wherein: the aging prevention circuitry nullifies any gate-to-source voltage on the driving transistors;the driving transistors in the tristate buffer stage includes: a first pull-down transistor with a gate terminal connected to the input selection stage and a first pull-up transistor with a gate terminal connected to the input selection stage; andthe tristate buffer stage further comprises a level restoring circuit that is coupled to the gate terminal of the first pull-up transistor. 9. A method of operating an multiplexing circuit on an integrated circuit, comprising: with first input selection transistors, selectively passing through a selected data signal to a first intermediate node by controlling select signals;with second input selection transistors, selectively passing through the selected data signal to a second intermediate node that is different than the first intermediate node by controlling the select signals;with a first tie-off transistor, selectively driving the first intermediate node to a positive power supply voltage level by controlling an enable signal that is different than the select signals;with a second tie-off transistor, selectively driving the second intermediate node to a ground power supply voltage level by controlling the enable signal;with a first pull-up transistor, receiving the selected data signal from the first input selection transistors;with a first pull-down transistor, receiving the selected data signal from the second input selection transistors;at a gate terminal of a second pull-up transistor, receiving a first voltage signal from the first pull-up transistor;at a gate terminal of a second pull-down transistor, receiving a second voltage signal from the first pull-down transistor;with a third tie-off transistor, selectively driving the gate terminal of the second pull-up transistor to the positive power supply voltage level; andwith a fourth tie-off transistor, selectively driving the gate terminal of the second pull-down transistor to the ground power supply voltage level. 10. The method of claim 9, further comprising: selectively shorting the first and second intermediate nodes with a transmission gate. 11. The method of claim 9, further comprising: selectively shorting the first pull-up transistor to the first pull-down transistor with a transmission gate.
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이 특허에 인용된 특허 (9)
Liu, Jonathan H.; Kang, Wonjae L., Body bias compensation for aged transistors.
Teramoto, Yuki; Haraguchi, Yoshinori, Semiconductor device, method for controlling the same, and data processing system including semiconductor device.
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