초록 ▼

Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having a reduced bottom contact resistance. A multilayered bottom doped region having alternating doped layers and doped sacrificial layers is formed on a substrate. One or more cavities are f

Embodiments are directed to a method and resulting structures for a vertical field effect transistor (VFET) having a reduced bottom contact resistance. A multilayered bottom doped region having alternating doped layers and doped sacrificial layers is formed on a substrate. One or more cavities are formed by removing portions of the doped sacrificial layers. A bottom contact is formed over the multilayered bottom doped region. The bottom contact includes one or more conductive flanges that fill the cavities.

대표청구항 ▼

1. A method for forming a semiconductor device, the method comprising: forming a multilayered bottom doped region comprising alternating doped layers and doped sacrificial layers on a substrate;forming one or more cavities by removing portions of the doped sacrificial layers; andforming a bottom con

1. A method for forming a semiconductor device, the method comprising: forming a multilayered bottom doped region comprising alternating doped layers and doped sacrificial layers on a substrate;forming one or more cavities by removing portions of the doped sacrificial layers; andforming a bottom contact over the multilayered bottom doped region, said bottom contact comprising one or more conductive flanges filling the cavities. 2. The method of claim 1 further comprising forming a semiconductor fin on a substrate and adjacent to the multilayered bottom doped region. 3. The method of claim 2 further comprising forming a conductive gate over a channel region of the semiconductor fin. 4. The method of claim 3 further comprising forming a bottom spacer between the multilayered bottom doped region and the conductive gate. 5. The method of claim 4, wherein the cavities extend beneath the conductive gate. 6. The method of claim 4, wherein the cavities do not extend beneath the conductive gate. 7. The method of claim 1, wherein forming the one or more cavities further comprises removing portions of a doped layer of the multilayered bottom doped region. 8. The method of claim 1, wherein the doped layers comprise silicon and the doped sacrificial layers comprise silicon germanium. 9. The method of claim 1, wherein the bottommost doped sacrificial layer of the multilayered bottom doped region comprises a first germanium content and the remaining doped sacrificial layers of the multilayered bottom doped region comprise a second germanium content. 10. The method of claim 9, wherein first germanium content is higher than the second germanium content. 11. The method of claim 1, wherein forming one or more cavities by removing portions of the doped sacrificial layers further comprises laterally etching the doped sacrificial layers. 12. The method of claim 11, wherein the lateral etch comprises a gas phase etch process by hydrochloride (HCl) or a wet etch process by hydrogen peroxide (H2O2) or SC1. 13. A method for forming a semiconductor device, the method comprising: forming a semiconductor fin on a substrate;forming a multilayered bottom doped region comprising alternating doped layers and doped sacrificial layers on the substrate and adjacent to sidewalls of the semiconductor fin;forming a conductive gate over a channel region of the semiconductor fin;forming a bottom spacer between the conductive gate and the multilayered bottom doped region;doping a portion of the semiconductor fin between the bottom spacer and the substrate;forming one or more cavities by removing portions of the doped sacrificial layers; andforming a bottom contact over the multilayered bottom doped region, said bottom contact comprising one or more conductive flanges filling the cavities;wherein the one or more conductive flanges extend from the bottom contact to the doped portion of the semiconductor fin. 14. The method of claim 13, wherein the doped layers comprise silicon and the doped sacrificial layers comprise silicon germanium. 15. The method of claim 13, wherein the bottommost doped sacrificial layer of the multilayered bottom doped region comprises a first germanium content and the remaining doped sacrificial layers of the multilayered bottom doped region comprise a second germanium content. 16. A method for forming a semiconductor device, the method comprising: forming a semiconductor fin on a substrate;forming a multilayered bottom doped region comprising alternating doped layers and doped sacrificial layers on the substrate and adjacent to sidewalls of the semiconductor fin;forming a conductive gate over a channel region of the semiconductor fin;forming a bottom spacer between the conductive gate and the multilayered bottom doped region;doping a portion of the semiconductor fin between the bottom spacer and the substrate;forming one or more cavities by removing portions of the doped sacrificial layers; andforming a bottom contact over the multilayered bottom doped region, said bottom contact comprising one or more conductive flanges filling the cavities;wherein a portion of the doped sacrificial layers remains between the one or more conductive flanges and the doped portion of the semiconductor fin. 17. The method of claim 16, wherein the doped layers comprise silicon and the doped sacrificial layers comprise silicon germanium. 18. The method of claim 16, wherein the bottommost doped sacrificial layer of the multilayered bottom doped region comprises a first germanium content and the remaining doped sacrificial layers of the multilayered bottom doped region comprise a second germanium content.