Method for manufacturing SiC wafer fit for integration with power device manufacturing technology
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
C30B-023/02
H01L-021/02
C30B-029/36
C30B-025/08
C30B-025/16
C30B-025/20
C30B-033/10
출원번호
US-0061959
(2016-03-04)
등록번호
US-10002760
(2018-06-19)
발명자
/ 주소
Hansen, Darren
Loboda, Mark
Manning, Ian
Moeggenborg, Kevin
Mueller, Stephan
Parfeniuk, Christopher
Quast, Jeffrey
Torres, Victor
Whiteley, Clinton
출원인 / 주소
DOW SILICONES CORPORATION
대리인 / 주소
Womble Bond Dickinson (US) LLP
인용정보
피인용 횟수 :
0인용 특허 :
57
초록▼
A method for producing silicon carbide substrates fit for epitaxial growth in a standard epitaxial chamber normally used for silicon wafers processing. Strict limitations are placed on any substrate that is to be processed in a chamber normally used for silicon substrates, so as to avoid contaminati
A method for producing silicon carbide substrates fit for epitaxial growth in a standard epitaxial chamber normally used for silicon wafers processing. Strict limitations are placed on any substrate that is to be processed in a chamber normally used for silicon substrates, so as to avoid contamination of the silicon wafers. To take full advantage of standard silicon processing equipment, the SiC substrates are of diameter of at least 150 mm. For proper growth of the SiC boule, the growth crucible is made to have interior volume that is six to twelve times the final growth volume of the boule. Also, the interior volume of the crucible is made to have height to width ratio of 0.8 to 4.0. Strict limits are placed on contamination, particles, and defects in each substrate.
대표청구항▼
1. A method for manufacturing SiC crystal to a grown volume, comprising: i. introducing a mixture comprising silicon chips into a reaction cell, the reaction cell being made of graphite and having cylindrical interior of internal volume in the range of from six to twelve times the grown volume of th
1. A method for manufacturing SiC crystal to a grown volume, comprising: i. introducing a mixture comprising silicon chips into a reaction cell, the reaction cell being made of graphite and having cylindrical interior of internal volume in the range of from six to twelve times the grown volume of the SiC crystal;ii. placing a silicon carbide seed crystal inside the reaction cell adjacent to a lid of the reaction cell;iii. sealing the cylindrical reaction cell using the lid;iv. surrounding the reaction cell with graphite insulation;v. introducing the cylindrical reaction cell into a vacuum furnace;vi. evacuating the vacuum furnace;vii. filling the vacuum furnace with a gas mixture comprising inert gas;viii. heating the cylindrical reaction cell in the vacuum furnace to a temperature in the range from 1975° C. to 2500° C.;ix. reducing the pressure in the vacuum furnace to from 0.05 torr to less than 50 torr;x. flowing nitrogen gas configured to introduce nitrogen donor concentration larger than 3E18/cm2, and up to 6E18/cm2; and,xi. allowing for sublimation of silicon and carbon species and condensation of vapors on the seed and stopping the sublimation when the grown volume of the SiC crystal reaches one twelfth to one sixth of the internal volume of the reaction cell and the SiC crystal is sufficiently large to yield ten or more substrates. 2. The method of claim 1, wherein the cylindrical graphite reaction cell has a volume of from 4000 cm3 to 16000 cm3. 3. The method of claim 2, wherein the cylindrical graphite reaction cell has a ratio of inner height to inner diameter in the range from 0.8 to 4.0. 4. The method of claim 1, wherein the seed is placed inside the reaction cell without physical attachment to the reaction cell or the lid, thereby enabling the seed to freely expand. 5. The method of claim 1, wherein the seed is placed on a shelf inside the reaction cell. 6. The method of claim 1, further comprising slicing the crystal in a direction such that resulting wafers have surface that is tilted from 3.5 to 4.4 degrees away from c-axis toward direction. 7. The method of claim 6, further comprising grinding and polishing each wafer to thereby reduce thickness of each wafer to an average thickness in the range of 365 μm to 675 μm. 8. The method of claim 7, further comprising grinding circumferential edge of each wafer to create a beveled edge. 9. The method of claim 8, wherein grinding and polishing each wafer is performed to generate a total thickness variation in the range of from 0.5 μm to 5 μm, and warp in the range of from 1 um to 40 μm. 10. The method of claim 9, further comprising cleaning the wafers to provide surface metal contamination level measured by TXRF on either a C face or an Si face of the substrate as the sum of the areal density of Na, Mg, Al, Ca, K, Mg from 25E10/cm2 to 250E10/cm2 and the sum of areal density of atoms P, Ni, Fe, Co, Cu, Mn from 10E10/cm2 to 150E10/cm2 wherein cleaning the wafers comprises dipping the wafers in ultrasonic cleaning tank having caustic surfactants having a pH of from greater than 9 to less than 12, and mixed in de-ionized water. 11. The method of claim 1, wherein stopping the sublimation is done when the grown volume of the SiC crystal reaches one third of the internal volume of the reaction cell. 12. The method of claim 10, wherein the concentration of the caustic surfactant is from 0.5 to 10%. 13. The method of claim 12, further comprising performing rinsing and spin-dry procedures. 14. The method of claim 13, further comprising cleaning the substrates after polishing using acidic solution having pH of less than 4, so as to remove particles and residual metallic contamination. 15. The method of claim 14, further comprising scrubbing the wafers using polyvinyl alcohol brush. 16. The method of claim 15, wherein median areal density of crystalline dislocations in the substrate is between 1/cm2 and 2600/cm2. 17. The method of claim 16, wherein aggregated scratch length measured on fabrication surface of each wafer is in a range from 5 μm to 5000 μm. 18. The method of claim 17, wherein a particle count in each wafer is from 5 to 500 total particles each having a diameter range from 0.5 μm to 10 μm. 19. The method of claim 18, further comprising loading the substrates into epitaxial deposition chamber and depositing epitaxial layer of SiC on the wafers. 20. The method of claim 19, wherein after loading the substrate but prior to depositing epitaxial layers, cleaning the substrates by heating the substrates to an elevated temperature and flowing a gas mixture of hydrogen and hydrogen chloride into the epitaxial deposition chamber. 21. The method of claim 20, wherein the epitaxial layers are deposited on the substrates using a gas mixture which included at least one gas with a chlorine atom. 22. The method of claim 19, wherein prior to loading the substrates, the surface metal contamination level of each substrate, is measured by TXRF on either a C face or an Si face of the substrate, and the sum of the areal density of Na, Mg, Al, Ca, K, Mg is from 25E10/cm2 to 250E10/cm2 and a sum of areal density of atoms P, Ni, Fe, Co, Cu, Mn is from 10E10/cm2 to 150E10/cm2. 23. The substrate of claim 22, wherein when the SiC homoepitaxial layer is etched in molten KOH and measured at 19 sites distributed across a surface, the median areal density of screw dislocations is in the range of from 0/cm2 to 400/cm2, and at least one site measured zero screw dislocations, and median areal density of basal plane dislocations is in the range of from 0/cm2 to 20/cm2, and at least one site measured zero basal plane dislocations. 24. The method of claim 4, wherein a setback space is provided between the seed and the lid, enabling the seed to freely move vertically, wherein the seeds' vertical movement is bounded to a predefined distance amount such that back surface of the seed never touches the surface of the lid.
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