[특허]Techniques for optimizing dual track routing

Techniques for optimizing dual track routing 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H05K-001/11 G06F-017/50 H05K-001/02
출원번호	US-0507632 (2014-10-06)
등록번호	US-9996653 (2018-06-12)
발명자 / 주소	Shen, Lin Xiong, Yongming Mahmood, Shahbaz De Nicolo, Maurilio
출원인 / 주소	CISCO TECHNOLOGY, INC.
대리인 / 주소	Polsinelli PC
인용정보	피인용 횟수 : 0 인용 특허 : 72

초록 ▼

The subject technology provides a method and apparatus for performing dual track routing. A pair of signal traces is routed in between two rows of contacts and at least one of the signal traces is modified to satisfy a routing restriction. The modification of the signal trace includes three trace se

대표청구항 ▼

1. An apparatus comprising: a printed circuit board (PCB) including: a first set of vias and a second set of vias, wherein one via of the first set of vias is a back-drilled via and another via of the second set of vias is not a back-drilled via;at least one routing channel between the first set of vias and the second set of vias; anda first conductive trace and a second conductive trace routed in the at least one routing channel,wherein, the first conductive trace includes a first trace segment directed toward the second conductive trace to increase a distance between the first conductive trace and the one via along a second trace segment of the first conductive trace,the second conductive trace includes a third trace segment (i) extending along the second trace segment and the another via, and (ii) having a decreased width to maintain a distance between the first conductive trace and the second conductive trace,the first conductive trace includes a fourth trace segment directed away from the second conductive trace,the second conductive trace includes a fifth trace segment extending (i) from the third trace segment, (ii) toward the first conducting trace and (iii) substantially parallel to the fourth trace segment,the first conductive trace and the second conductive trace are separated by a spacing distance, andthe spacing distance is a function of a trace width of the first conductive trace and a trace width of the second conductive trace. 2. The apparatus of claim 1, wherein, the second trace segment extends (i) between the first trace segment and the fourth trace segment, and (ii) substantially parallel to the second conductive trace. 3. The apparatus of claim 2, wherein the first conductive trace is associated with a trace width, and wherein the second trace segment is associated with a segment width, the segment width being smaller than the trace width. 4. The apparatus of claim 1, wherein, the second trace segment is shorter in length than the third trace segment. 5. The apparatus of claim 1, wherein the first set of vias and the second set of vias correspond to an array of contacts configured to receive an integrated circuit having a ball-grid array package. 6. The apparatus of claim 1, wherein a portion of the first conductive trace is a curved portion. 7. The apparatus of claim 6, wherein the first conductive trace is associated with a trace width, and wherein the curved portion is associated with a segment width, the segment width being smaller than the trace width. 8. The apparatus of claim 2, wherein the first trace segment and the fourth trace segment are each associated with a first segment width, and wherein the second trace segment is associated with a second segment width, the second segment width being smaller than the first segment width.

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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
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A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

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Techniques for optimizing dual track routing 원문보기

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Techniques for optimizing dual track routing 원문보기

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