MOS capacitors for variable capacitor arrays and methods of forming the same
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G05F-001/10
G05F-003/24
G05F-003/20
H03H-007/01
H03H-007/12
H01L-029/66
H01L-029/94
H03H-007/40
H03H-007/46
출원번호
US-0085572
(2016-03-30)
등록번호
US-10042376
(2018-08-07)
발명자
/ 주소
Gahlsdorf, Rien
Bao, Jianwen
출원인 / 주소
TDK Corporation
대리인 / 주소
Nixon Peabody LLP
인용정보
피인용 횟수 :
0인용 특허 :
40
초록▼
A capacitor structure is described. The capacitor structure includes a substrate, a plurality of source/drain regions formed in the substrate, and a plurality of gates formed above the substrate. The plurality of gates formed above the substrate such that each of the plurality of gates is formed bet
A capacitor structure is described. The capacitor structure includes a substrate, a plurality of source/drain regions formed in the substrate, and a plurality of gates formed above the substrate. The plurality of gates formed above the substrate such that each of the plurality of gates is formed between each pair of source/drain regions of the plurality of source/drain regions to form a channel between each pair of source/drain regions.
대표청구항▼
1. A capacitor structure comprising: a substrate;a first plurality of source/drain regions formed in said substrate; anda first plurality of gates formed above said substrate such that each of said first plurality of gates is formed between each pair of source/drain regions of said first plurality o
1. A capacitor structure comprising: a substrate;a first plurality of source/drain regions formed in said substrate; anda first plurality of gates formed above said substrate such that each of said first plurality of gates is formed between each pair of source/drain regions of said first plurality of source/drain regions to form a channel between said each pair of source/drain regions, each source/drain region of said first plurality of source/drain regions formed between a pair of gates of said first plurality of gates is a source for a first gate of said pair of gates and a drain for a second gate of said pair of gates;wherein said substrate, said first plurality of source/drain regions and said first plurality of gates are interconnected to form a first capacitor. 2. The capacitor structure of claim 1, wherein said substrate is a silicon-on-insulator substrate. 3. The capacitor structure of claim 1, wherein said substrate includes a second plurality of source/drain regions and a second plurality of gates interconnected to form at least a second capacitor, at least said first capacitor and said second capacitor connected in an anti-series configuration. 4. The capacitor structure of claim 1, wherein said substrate includes a second plurality of source/drain regions and a second plurality of gates, said first plurality of source/drain regions, said second plurality of source/drain regions, said first plurality of gates, and said second plurality of gates are interconnected to form a variable capacitor cell of a variable capacitor array. 5. The capacitor structure of claim 4, wherein the variable capacitor cell is part of an integrated circuit. 6. The capacitor structure of claim 1, wherein said substrate includes at least a second plurality of source/drain regions and at least a second plurality of gates, at least said second plurality of source/drain regions and at least said second plurality of gates are interconnected to form a plurality of variable capacitor cells of a variable capacitor array. 7. The capacitor structure of claim 1, wherein said substrate includes a second plurality of source/drain regions and a second plurality of gates, said first plurality of source/drain regions, said second plurality of source/drain regions, said first plurality of gates, and said second plurality of gates are interconnected to form a variable capacitor cell of a variable capacitor array. 8. A method to form a plurality of capacitors comprising: forming a first plurality of source/drain regions in a substrate;forming a first plurality of gates above said substrate such that each of said first plurality of gates is formed between each pair of source/drain regions of said first plurality of source/drain regions to form a channel between said each pair of source/drain regions, each source/drain region of said first plurality of source/drain regions formed between a pair of gates of said first plurality of gates is a source for a first gate of said pair of gates and a drain for a second gate of said pair of gates; andforming connections between said first plurality of source/drain regions and said first plurality of gates to form a first capacitor. 9. The method of claim 8, wherein said substrate is a silicon-on-insulator substrate. 10. The method of claim 8, further comprising: forming a second plurality of source/drain regions in said substrate;forming a second plurality of gates above said substrate such that each of said second plurality of gates is formed between each pair of source/drain regions of said second plurality of source/drain regions to form a channel between said each pair of source/drain regions;forming connections between said second plurality of source/drain regions and said second plurality of gates to form at least a second capacitor; andforming connections between at least said first capacitor and said second capacitor to form one or more pairs of capacitors connected in an anti-series configuration. 11. The method of claim 8, further comprising: forming a second plurality of source/drain regions in said substrate;forming a second plurality of gates above said substrate such that each of said second plurality of gates is formed between each pair of source/drain regions of said second plurality of source/drain regions to form a channel between said each pair of source/drain regions;forming connections between said first plurality of source/drain regions, said first plurality of gates, said second plurality of source/drain regions, and said second plurality of gates to form a variable capacitor cell of a variable capacitor array. 12. The capacitor structure of claim 8, further comprising: forming a second plurality of source/drain regions in said substrate;forming a second plurality of gates above said substrate such that each of said second plurality of gates is formed between each pair of source/drain regions of said second plurality of source/drain regions to form a channel between said each pair of source/drain regions;forming connections between at least said second plurality of source/drain regions and said second plurality of gates to form a plurality of variable capacitor cells of a variable capacitor array. 13. An integrated circuit comprising: a substrate;a first plurality of source/drain regions formed in said substrate; anda first plurality of gates formed above said substrate such that each of said first plurality of gates is formed between each pair of source/drain regions of said first plurality of source/drain regions to form a channel between said each pair of source/drain regions, each source/drain region of said first plurality of source/drain regions formed between a pair of gates of said first plurality of gates is a source for a first gate of said pair of gates and a drain for a second gate of said pair of gates;wherein said substrate, said first plurality of source/drain regions and said first plurality of gates are interconnected to form a first capacitor. 14. The integrated circuit of claim 13, wherein said substrate is a silicon-on-insulator substrate. 15. The integrated circuit of claim 13, wherein said substrate includes a second plurality of source/drain regions and a second plurality of gates interconnected to form at least a second capacitor, at least said first capacitor and said second capacitor connected in an anti-series configuration. 16. The integrated circuit of claim 13, wherein said substrate includes a second plurality of source/drain regions and a second plurality of gates, said first plurality of source/drain regions, said second plurality of source/drain regions, said first plurality of gates, and said second plurality of gates are interconnected to form a variable capacitor cell of a variable capacitor array. 17. The integrated circuit of claim 16, further comprising a bias voltage generator configured to generate a bias voltage for each one of said plurality of variable capacitor cells of said variable capacitor array. 18. The integrated circuit of claim 17, further comprising an interface configured to receive a control signal for said bias voltage generator used to adjust a value of said bias voltage for each one of said plurality of variable capacitor cells of said variable capacitor array. 19. The integrated circuit of claim 18, wherein said interface is a Mobile Industry Processor Interface radio front end interface. 20. The integrated circuit of claim 13, wherein said substrate includes at least a second plurality of source/drain regions and at least a second plurality of gates, at least said second plurality of source/drain regions and at least said second plurality of gates are interconnected to form a plurality of variable capacitor cells of a variable capacitor arrays.
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