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Method of manufacturing a semiconductor device including through silicon plugs

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/00
  • H01L-021/768
  • H01L-033/64
  • H01L-021/683
  • H01L-023/48
  • H01L-033/48
  • H01L-033/62
  • H01L-033/00
  • H01L-021/3065
  • H01L-021/48
  • H01L-023/14
  • H01L-023/498
  • H01L-023/00
출원번호 US-0069474 (2016-03-14)
등록번호 US-10049931 (2018-08-14)
발명자 / 주소
  • Yu, Chen-Hua
  • Chang, Hung-Pin
  • Lin, Yung-Chi
  • Yu, Chia-Lin
  • Hung, Jui-Pin
  • Hwang, Chien Ling
출원인 / 주소
  • Taiwan Semicondutor Manufacturing Company, Ltd.
대리인 / 주소
    Haynes and Boone, LLP
인용정보 피인용 횟수 : 0  인용 특허 : 38

초록

A method of making a semiconductor device is provided including forming a first opening and a second opening in a first surface of a substrate. A conductive material is formed in the first opening and in the second opening and over the first surface in the first region of the substrate between the o

대표청구항

1. A method of making a semiconductor device, the method comprising: forming a first opening, a second opening, and a third opening in a first surface of a substrate, wherein a first region of the substrate having the first surface interposes the first and second openings and a second region of the

이 특허에 인용된 특허 (38)

  1. Chen,Chien Hua; Chen,Zhizhang; Meyer,Neal W., 3D interconnect with protruding contacts.
  2. Matsui,Satoshi, Chip and multi-chip semiconductor device using thereof and method for manufacturing same.
  3. Pogge, H. Bernhard; Yu, Roy; Prasad, Chandrika; Narayan, Chandrasekhar, Chip and wafer integration process using vertical connections.
  4. Honn ; James J. ; Stuby ; Kenneth P., Electrical package for LSI devices and assembly process therefor.
  5. Alley, Randall G.; Deane, Philip A.; Koester, David A.; Schneider, Thomas Peter; von Windheim, Jesko, Electronic assemblies providing active side heat pumping.
  6. Kano Gota,JPX ; Shimada Yasuhiro,JPX ; Hayashi Shinichiro,JPX ; Arita Koji ; Paz de Araujo Carlos A. ; Cuchiaro Joseph D. ; McMillan Larry D., Ferroelectric flat panel displays.
  7. Chanchani,Rajen, Heterogeneously integrated microsystem-on-a-chip.
  8. Chudzik, Michael Patrick; Dennard, Robert H.; Divakaruni, Rama; Furman, Bruce Kenneth; Jammy, Rajarao; Narayan, Chandrasekhar; Purushothaman, Sampath; Shepard, Jr., Joseph F.; Topol, Anna Wanda, High density chip carrier with integrated passive devices.
  9. Chudzik,Michael Patrick; Dennard,Robert H.; Divakaruni,Rama; Furman,Bruce Kenneth; Jammy,Rajarao; Narayan,Chandrasekhar; Purushothaman,Sampath; Shepard, Jr.,Joseph F.; Topol,Anna Wanda, High density chip carrier with integrated passive devices.
  10. Siniaguine, Oleg, Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate.
  11. Siniaguine Oleg, Integrated circuits and methods for their fabrication.
  12. Siniaguine, Oleg, Integrated circuits and methods for their fabrication.
  13. Siniaguine, Oleg, Integrated circuits and methods for their fabrication.
  14. Siniaguine, Oleg, Integrated circuits and methods for their fabrication.
  15. Savastiouk,Sergey; Halahan,Patrick B.; Kao,Sam, Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities.
  16. Tadatomo Suga JP, Interconnect structure for stacked semiconductor device.
  17. Matsui,Kuniyasu, Intermediate chip module, semiconductor device, circuit board, and electronic device.
  18. Lee, Sung Jun; Hwang, Woong Lin; Choi, Sang Hyun; Lim, Chang Hyun; Park, Ho Joon; Choi, Seog Moon, LED package using Si substrate and fabricating method thereof.
  19. Eilert,Sean S., Method and apparatus for generating a device ID for stacked devices.
  20. Valluri R. Rao ; Jeffrey K. Greason ; Richard H. Livengood, Method for distributing a clock on the silicon backside of an integrated circuit.
  21. Black Charles Thomas ; Burghartz Joachim Norbert ; Tiwari Sandip ; Welser Jeffrey John, Method for making three dimensional circuit integration.
  22. Tadatomo Suga JP, Method for manufacturing an interconnect structure for stacked semiconductor device.
  23. Redwine Donald J. (Houston TX), Method of interconnect in an integrated circuit.
  24. Jackson, Timothy L.; Murphy, Tim E., Methods of fabrication of semiconductor dice having back side redistribution layer accessed using through-silicon vias and assemblies thereof.
  25. Thomas,Jochen; Schoenfeld,Olaf, Multi-chip device and method for producing a multi-chip device.
  26. Farnworth, Warren M.; Wood, Alan G.; Hiatt, William M.; Wark, James M.; Hembree, David R.; Kirby, Kyle K.; Benson, Pete A., Multi-dice chip scale semiconductor components and wafer level methods of fabrication.
  27. Gilmour Richard J. (Liberty Hill TX) Schrottke Gustav (Austin TX), Multiprocessor module packaging.
  28. Siniaguine Oleg ; Savastiouk Sergey, Package of integrated circuits and vertical integration.
  29. Siniaguine, Oleg; Savastiouk, Sergey, Packaging of integrated circuits and vertical integration.
  30. Chen, Hsing, Packaging of light-emitting diode.
  31. Savastiouk,Sergey; Halahan,Patrick B.; Kao,Sam, Packaging substrates for integrated circuits and soldering methods.
  32. Bertagnolli Emmerich,DEX ; Klose Helmut,DEX, Process for producing semiconductor components between which contact is made vertically.
  33. Kim,Sarah E.; List,R. Scott; Kellar,Scot A., Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices.
  34. Jackson, Timothy L.; Murphy, Tim E., Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies.
  35. Jackson,Timothy L.; Murphy,Tim E., Semiconductor dice having back side redistribution layer accessed using through-silicon vias, methods.
  36. Fey,Kate E.; Byers,Charles L.; Mandell,Lee J., Space-saving packaging of electronic circuits.
  37. Kong, Sik On, Three dimensional IC package module.
  38. Rumer, Christopher L.; Zarbock, Edward A., Through silicon via, folded flex microelectronic package.
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