Apparatus and methods for MOS capacitor structures for variable capacitor arrays
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H03B-001/00
H03K-005/00
G05F-003/24
G05F-003/20
H01L-029/66
H01L-027/08
H01L-029/94
H01L-027/12
H01L-029/93
출원번호
US-0085863
(2016-03-30)
등록번호
US-10073482
(2018-09-11)
발명자
/ 주소
Gahlsdorf, Rien
Bao, Jianwen
출원인 / 주소
TDK Corporation
대리인 / 주소
Nixon Peabody LLP
인용정보
피인용 횟수 :
0인용 특허 :
40
초록▼
A capacitor structure is described. A capacitor structure including a substrate and at least one device formed on the substrate. The device including first and second sections. Each of the first and second sections including a plurality of source/drain regions formed in the substrate and a plurality
A capacitor structure is described. A capacitor structure including a substrate and at least one device formed on the substrate. The device including first and second sections. Each of the first and second sections including a plurality of source/drain regions formed in the substrate and a plurality of gates formed above the substrate such that each of the plurality of gates is formed between each pair of source/drain regions to form a section channel between each pair of source/drain regions. The plurality of gates of the first and second sections are coupled with each other.
대표청구항▼
1. A capacitor structure comprising: a substrate; andat least one capacitor formed on said substrate, each capacitor including a first section and a second section, said first section including: a first plurality of source/drain regions formed in said substrate, anda first plurality of gates formed
1. A capacitor structure comprising: a substrate; andat least one capacitor formed on said substrate, each capacitor including a first section and a second section, said first section including: a first plurality of source/drain regions formed in said substrate, anda first plurality of gates formed above said substrate such that each of said first plurality of gates is formed between each pair of source/drain regions of said first plurality of source/drain regions to form a first section channel between said each pair of source/drain regions, each source/drain region formed between a pair of gates of the first plurality of gates is a source for a first gate of said pair of gates and a drain for a second gate of said pair of gates,said second section including: a second plurality of source/drain regions formed in said substrate, anda second plurality of gates formed above said substrate such that each of said second plurality of gates is formed between each pair of source/drain regions of said second plurality of source/drain regions to form a second section channel between said each pair of source/drain regions, each source/drain region formed between a pair of gates of the second plurality of gates is a source for a first gate of said pair of gates and a drain for a second gate of said pair of gates,wherein said first plurality of gates are coupled with said second plurality of gates. 2. The capacitor structure of claim 1, wherein said substrate is a silicon-on-insulator substrate. 3. The capacitor structure of claim 1, wherein said substrate includes at least a second capacitor including a third section and a fourth section, said third section including a third plurality of source/drain regions formed in said substrate and a third plurality of gates formed above said substrate such that each of said third plurality of gates is formed between each pair of source/drain regions of said third plurality of source/drain regions to form a third section channel between said each pair of source/drain regions, said fourth section including a fourth plurality of source/drain regions and a fourth plurality of gates formed above said substrate such that each of said fourth plurality of gates is formed between each pair of source/drain regions of said fourth plurality of source/drain regions to form a fourth section channel between said each pair of source/drain regions, said first section, said second section, said third section, and said fourth section are interconnected to form a pair of capacitors connected in an anti-series configuration. 4. The capacitor structure of claim 1, wherein said substrate includes at least a second capacitor including a third section and a fourth section, said third section including a third plurality of source/drain regions formed in said substrate and a third plurality of gates formed above said substrate such that each of said third plurality of gates is formed between each pair of source/drain regions of said third plurality of source/drain regions to form a third section channel between said each pair of source/drain regions, said fourth section including a fourth plurality of source/drain regions and a fourth plurality of gates formed above said substrate such that each of said fourth plurality of gates is formed between each pair of source/drain regions of said fourth plurality of source/drain regions to form a fourth section channel between said each pair of source/drain regions, said first section, said second section, said third section, and said fourth section are interconnected to form a variable capacitor cell of a variable capacitor array. 5. The capacitor structure of claim 4, wherein the variable capacitor cell is part of an integrated circuit. 6. The capacitor structure of claim 1, wherein said substrate includes at least a second capacitor including a third section and a fourth section, said third section including a third plurality of source/drain regions formed in said substrate and a third plurality of gates formed above said substrate such that each of said third plurality of gates is formed between each pair of source/drain regions of said third plurality of source/drain regions to form a third section channel between said each pair of source/drain regions, said fourth section including a fourth plurality of source/drain regions and a fourth plurality of gates formed above said substrate such that each of said fourth plurality of gates is formed between each pair of source/drain regions of said fourth plurality of source/drain regions to form a fourth section channel between said each pair of source/drain regions, said first section, said second section, said third section, and said fourth section are interconnected to form a plurality of variable capacitor cells of a variable capacitor array. 7. A method to form a plurality of capacitors comprising: for each capacitor of said plurality of capacitors: forming a plurality of source/drain regions in a substrate;forming a first plurality of gates above said substrate such that each of said first plurality of gates is formed between each pair of source/drain regions of said first plurality of source/drain regions to form a first section channel between said each pair of source/drain regions, each source/drain region formed between a pair of gates of the first plurality of gates is a source for a first gate of said pair of gates and a drain for a second gate of said pair of gates; andforming a second plurality of gates above said substrate such that each of said second plurality of gates is formed between each pair of source/drain regions of said second plurality of source/drain regions to form a second section channel between said each pair of source/drain regions, each source/drain region formed between a pair of gates of the second plurality of gates is a source for a first gate of said pair of gates and a drain for a second gate of said pair of gates, wherein said first plurality of gates are coupled with said second plurality of gates. 8. The method of claim 7, wherein said substrate is a silicon-on-insulator substrate. 9. The method of claim 7, further comprising: forming a third plurality of source/drain regions formed in said substrate;forming a third plurality of gates formed above said substrate such that each of said third plurality of gates is formed between each pair of source/drain regions of said third plurality of source/drain regions to form a third section channel between said each pair of source/drain regions;forming a fourth plurality of source/drain regions;forming a fourth plurality of gates formed above said substrate such that each of said fourth plurality of gates is formed between each pair of source/drain regions of said fourth plurality of source/drain regions to form a fourth section channel between said each pair of source/drain regions; andforming connections between said first, said second, said third and said fourth plurality of source/drain regions and said first plurality, said second plurality, said third plurality and said fourth plurality of gates to form a pair of capacitors connected in an anti-series configuration. 10. The method of claim 7, further comprising: forming a third plurality of source/drain regions formed in said substrate;forming a third plurality of gates formed above said substrate such that each of said third plurality of gates is formed between each pair of source/drain regions of said third plurality of source/drain regions to form a third section channel between said each pair of source/drain regions;forming a fourth plurality of source/drain regions;forming a fourth plurality of gates formed above said substrate such that each of said fourth plurality of gates is formed between each pair of source/drain regions of said fourth plurality of source/drain regions to form a fourth section channel between said each pair of source/drain regions; andforming connections between said first, said second, said third and said fourth plurality of source/drain regions and said first plurality, said second plurality, said third plurality and said fourth plurality of gates to form a variable capacitor cell of a variable capacitor array. 11. The capacitor structure of claim 7, further comprising: forming a third plurality of source/drain regions formed in said substrate;forming a third plurality of gates formed above said substrate such that each of said third plurality of gates is formed between each pair of source/drain regions of said third plurality of source/drain regions to form a third section channel between said each pair of source/drain regions;forming a fourth plurality of source/drain regions;forming a fourth plurality of gates formed above said substrate such that each of said fourth plurality of gates is formed between each pair of source/drain regions of said fourth plurality of source/drain regions to form a fourth section channel between said each pair of source/drain regions; andforming connections between said first, said second, said third and said fourth plurality of source/drain regions and said first plurality, said second plurality, said third plurality and said fourth plurality of gates to form a plurality of variable capacitor cells of a variable capacitor array. 12. An integrated circuit comprising: a substrate; andat least one capacitor formed on said substrate, each of said capacitor including a first section and a second section, said first section including: a first plurality of source/drain regions formed in said substrate, anda first plurality of gates formed above said substrate such that each of said first plurality of gates is formed between each pair of source/drain regions of said first plurality of source/drain regions to form a first section channel between said each pair of source/drain regions, each source/drain region formed between a pair of gates of the first plurality of gates is a source for a first gate of said pair of gates and a drain for a second gate of said pair of gatessaid second section including: a second plurality of source/drain regions formed in said substrate, anda second plurality of gates formed above said substrate such that each of said second plurality of gates is formed between each pair of source/drain regions of said second plurality of source/drain regions to form a second section channel between said each pair of source/drain regions, each source/drain region formed between a pair of gates of the second plurality of gates is a source for a first gate of said pair of gates and a drain for a second gate of said pair of gates,wherein said first plurality of gates are coupled with said second plurality of gates. 13. The integrated circuit of claim 12, wherein said substrate is a silicon-on-insulator substrate. 14. The integrated circuit of claim 12, wherein said substrate includes at least a second capacitor including a third section and a fourth section, said third section including a third plurality of source/drain regions formed in said substrate and a third plurality of gates formed above said substrate such that each of said third plurality of gates is formed between each pair of source/drain regions of said third plurality of source/drain regions to form a third section channel between said each pair of source/drain regions, said fourth section including a fourth plurality of source/drain regions and a fourth plurality of gates formed above said substrate such that each of said fourth plurality of gates is formed between each pair of source/drain regions of said fourth plurality of source/drain regions to form a fourth section channel between said each pair of source/drain regions, said first section, said second section, said third section, and said fourth section are interconnected to form a pair of capacitors connected in an anti-series configuration. 15. The integrated circuit of claim 12, wherein said substrate includes at least a second capacitor including a third section and a fourth section, said third section including a third plurality of source/drain regions formed in said substrate and a third plurality of gates formed above said substrate such that each of said third plurality of gates is formed between each pair of source/drain regions of said third plurality of source/drain regions to form a third section channel between said each pair of source/drain regions, said fourth section including a fourth plurality of source/drain regions and a fourth plurality of gates formed above said substrate such that each of said fourth plurality of gates is formed between each pair of source/drain regions of said fourth plurality of source/drain regions to form a fourth section channel between said each pair of source/drain regions, said first section, said second section, said third section, and said fourth section are interconnected to form a variable capacitor cell of a variable capacitor array. 16. The integrated circuit of claim 12, wherein said substrate includes at least a second capacitor including a third section and a fourth section, said third section including a third plurality of source/drain regions formed in said substrate and a third plurality of gates formed above said substrate such that each of said third plurality of gates is formed between each pair of source/drain regions of said third plurality of source/drain regions to form a third section channel between said each pair of source/drain regions, said fourth section including a fourth plurality of source/drain regions and a fourth plurality of gates formed above said substrate such that each of said fourth plurality of gates is formed between each pair of source/drain regions of said fourth plurality of source/drain regions to form a fourth section channel between said each pair of source/drain regions, said first section, said second section, said third section, and said fourth section are interconnected to form a plurality of variable capacitor cells of a variable capacitor array. 17. The integrated circuit of claim 16, further comprising a bias voltage generator configured to generate a bias voltage for each one of said plurality of variable capacitor cells of said variable capacitor array. 18. The integrated circuit of claim 17, further comprising an interface configured to receive a control signal for said bias voltage generator used to adjust a value of said bias voltage for each one of said plurality of variable capacitor cells of said variable capacitor array. 19. The integrated circuit of claim 18, wherein said interface is a Mobile Industry Processor Interface radio front end interface. 20. The integrated circuit of claim 12, wherein said substrate includes at least a second capacitor including a third section and a fourth section, said third section including a third plurality of source/drain regions formed in said substrate and a third plurality of gates formed above said substrate such that each of said third plurality of gates is formed between each pair of source/drain regions of said third plurality of source/drain regions to form a third section channel between said each pair of source/drain regions, said fourth section including a fourth plurality of source/drain regions and a fourth plurality of gates formed above said substrate such that each of said fourth plurality of gates is formed between each pair of source/drain regions of said fourth plurality of source/drain regions to form a fourth section channel between said each pair of source/drain regions, said first section, said second section, said third section, and said fourth section are interconnected to form a plurality of variable capacitor arrays.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (40)
Gallichio Michael J. (New Milford CT), Anti-parallel capacitor.
Alacoque, Jean-Claude, Galvanic isolation device for direct current electrical signals or electrical signals likely to include a direct current component.
Mucke Lars Henrik ; Hull Christopher Dennis ; Jansson Lars Gustaf, Method and apparatus for digitally controlling the capacitance of an integrated circuit device using mos-field effect transistors.
Carns, Timothy K.; Horvath, John L.; DeBruler, Lee J.; Westphal, Michael J., Method of fabricating high-performance capacitors in integrated MOS technologies.
Emesh Ismail T. (Cumberland CAX) Calder Iain D. (Kanata CAX) Ho Vu Q. (Kanata CAX) Jolly Gurvinder (Orleans CAX) Madsen Lynnette D. (Ottawa CAX), Structure and method of making a capacitor for an intergrated circuit.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.