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최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0497103 (2017-04-25) |
등록번호 | US-10074640 (2018-09-11) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
|
인용정보 | 피인용 횟수 : 0 인용 특허 : 589 |
A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in accordance with a dynamic array architecture so as to include a number of layout features. The number of layout features are linear-shaped and com
A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in accordance with a dynamic array architecture so as to include a number of layout features. The number of layout features are linear-shaped and commonly oriented. The layout is split into a number of sub-layouts for the level of the cell. Each of the number of layout features in the layout is allocated to any one of the number of sub-layouts. Also, the layout is split such that each sub-layout is independently fabricatable. The sub-layouts for the level of the cell are stored on a computer readable medium.
1. A semiconductor chip, comprising: a gate electrode level including a plurality of linear-shaped conductive structures defined to extend lengthwise in a first direction, the plurality of linear-shaped conductive structures positioned in accordance with a fixed pitch such that a distance as measure
1. A semiconductor chip, comprising: a gate electrode level including a plurality of linear-shaped conductive structures defined to extend lengthwise in a first direction, the plurality of linear-shaped conductive structures positioned in accordance with a fixed pitch such that a distance as measured in a second direction perpendicular to the first direction between first-direction-oriented-lengthwise-centerlines of any two of the plurality of linear-shaped conductive structures is substantially equal to an integer multiple of the fixed pitch,wherein the plurality of linear-shaped conductive structures includes a first set of linear-shaped conductive structures corresponding to a first sub-layout and a second set of linear-shaped conductive structures corresponding to a second sub-layout, the second set of linear-shaped conductive structures interleaved with the first set of linear-shaped conductive structures such that each linear-shaped conductive structure of the second set of linear-shaped conductive structures is separated from at least one adjacently located linear-shaped conductive structure of the first set of linear-shaped conductive structures by the fixed pitch as measured in the second direction between their first-direction-oriented-lengthwise-centerlines,wherein each of the plurality of linear-shaped conductive structures has a respective total length as measured in the first direction along its first-direction-oriented-lengthwise-centerline, and wherein the total length of each linear-shaped conductive structure of the first set of linear-shaped conductive structures is equal,wherein the first set of linear-shaped conductive structures is manufactured using a first mask, and wherein the second set of linear-shaped conductive structures is manufactured using a second mask different from the first mask, and wherein the first set of linear-shaped conductive structures is manufactured separately from the second set of linear-shaped conductive structures. 2. A semiconductor chip as recited in claim 1, wherein the integer multiple of the fixed pitch is equal to the fixed pitch multiplied by a whole number selected from a set of whole numbers including zero. 3. A semiconductor chip as recited in claim 2, wherein some of the plurality of linear-shaped conductive structures are substantially co-aligned such that the distance as measured in the second direction between their first-direction-oriented-lengthwise-centerlines is substantially equal to zero. 4. A semiconductor chip as recited in claim 1, wherein a spacing between at least one of the linear-shaped conductive structures of the first set of linear-shaped conductive structures and an adjacent one of the linear-shaped conductive structures of the second set of linear-shaped conductive structures is outside a fabrication capability of a semiconductor fabrication process. 5. A semiconductor chip as recited in claim 1, wherein the first set of linear-shaped conductive structures correspond to a first plurality of linear-shaped conductive structures, and wherein the second set of linear-shaped conductive structures correspond to a second plurality of linear-shaped conductive structures, andwherein the fixed pitch of the gate electrode level corresponds to a first pitch, andwherein the semiconductor chip further comprises a first interconnect level including a third plurality of linear-shaped conductive structures defined to extend lengthwise in the first direction, the third plurality of linear-shaped conductive structures positioned in accordance with a second pitch such that a distance as measured in the second direction perpendicular to the first direction between first-direction-oriented-lengthwise-centerlines of any two of the third plurality of linear-shaped conductive structures is substantially equal to an integer multiple of the second pitch,the first interconnect level including a fourth plurality of linear-shaped conductive structures defined to extend lengthwise in the first direction, the fourth plurality of linear-shaped conductive structures positioned in accordance with a third pitch such that a distance as measured in the second direction perpendicular to the first direction between first-direction-oriented-lengthwise-centerlines of any two of the fourth plurality of linear-shaped conductive structures is substantially equal to an integer multiple of the third pitch. 6. A semiconductor chip as recited in claim 5, wherein at least one of the second and third pitches is equal to the first pitch. 7. A semiconductor chip as recited in claim 5, wherein at least one of the second and third pitches is equal to the first pitch multiplied by a ratio of integers. 8. A semiconductor chip as recited in claim 1, wherein some linear-shaped conductive structures of the second set of linear-shaped conductive structures are co-aligned such that the distance as measured in the second direction perpendicular to the first direction between their first-direction-oriented-lengthwise-centerlines is equal to zero, and wherein adjacently positioned co-aligned linear-shaped conductive structures of the second set of linear-shaped conductive structures are separated from each other by a uniform end-to-end spacing as measured in the first direction. 9. A semiconductor chip as recited in claim 1, wherein the total length of each linear-shaped conductive structure of the second set of linear-shaped conductive structures is equal. 10. A semiconductor chip, comprising: a gate electrode level including a plurality of linear-shaped conductive structures defined to extend lengthwise in a first direction, the plurality of linear-shaped conductive structures positioned in accordance with a fixed pitch such that a distance as measured in a second direction perpendicular to the first direction between first-direction-oriented-lengthwise-centerlines of any two of the plurality of linear-shaped conductive structures is substantially equal to an integer multiple of the fixed pitch,wherein the plurality of linear-shaped conductive structure includes a first set of linear-shaped conductive structures corresponding to a first sub-layout and a second set of linear-shaped conductive structures corresponding to a second sub-layout, the second set of linear-shaped conductive structures interleaved with the first set of linear-shaped conductive structures such that each linear-shaped conductive structure of the second set of linear-shaped conductive structures is separated from at least one adjacently located linear-shaped conductive structure of the first set of linear-shaped conductive structures by the fixed pitch as measured between their first-direction-oriented-lengthwise-centerlines,wherein the total length of each linear-shaped conductive structure of the first set of linear-shaped conductive structures is equal to a first total length, and wherein the total length of each linear-shaped conductive structure of the second set of linear-shaped conductive structures is equal to a second total length, and wherein the first total length is different than the second total length,wherein the first set of linear-shaped conductive structures is manufactured using a first mask, and wherein the second set of linear-shaped conductive structures is manufactured using a second mask different from the first mask, and wherein the first set of linear-shaped conductive structures is manufactured separately from the second set of linear-shaped conductive structures. 11. A semiconductor chip as recited in claim 10, wherein some linear-shaped conductive structures of the second set of linear-shaped conductive structures are co-aligned such that the distance as measured in the second direction perpendicular to the first direction between their first-direction-oriented-lengthwise-centerlines is equal to zero, and wherein adjacently positioned co-aligned linear-shaped conductive structures of the second set of linear-shaped conductive structures are separated from each other by a uniform end-to-end spacing as measured in the first direction. 12. A semiconductor chip, comprising: a gate electrode level including a plurality of linear-shaped conductive structures defined to extend lengthwise in a first direction, the plurality of linear-shaped conductive structures positioned in accordance with a fixed pitch such that a distance as measured in a second direction perpendicular to the first direction between first-direction-oriented-lengthwise-centerlines of any two of the plurality of linear-shaped conductive structures is substantially equal to an integer multiple of the fixed pitch,wherein the plurality of linear-shaped conductive structure includes a first set of linear-shaped conductive structures corresponding to a first sub-layout and a second set of linear-shaped conductive structures corresponding to a second sub-layout and a third set of linear-shaped conductive structures corresponding to a third sub-layout,the first, second, and third sets of linear-shaped conductive structures positioned in a sequential manner in the second direction, wherein each linear-shaped conductive structure of the second set of linear-shaped conductive structures is positioned between at least one adjacently located linear-shaped conductive structure of the first set of linear-shaped conductive structures and at least one adjacently located linear-shaped conductive structure of the third set of linear-shaped conductive structures, and wherein each linear-shaped conductive structure of the third set of linear-shaped conductive structures is positioned between at least one adjacently located linear-shaped conductive structure of the second set of linear-shaped conductive structures and at least one adjacently located linear-shaped conductive structure of the first set of linear-shaped conductive structures,wherein the first set of linear-shaped conductive structures is manufactured using a first mask, and wherein the second set of linear-shaped conductive structures is manufactured using a second mask different from the first mask, and wherein the third set of linear-shaped conductive structures is manufactured using a third mask different from both the first mask and the second mask, andwherein the first set of linear-shaped conductive structures is manufactured separately from both the second and third sets of linear-shaped conductive structures, and wherein the second set of linear-shaped conductive structures is manufactured separately from both the first and third sets of linear-shaped conductive structures, and wherein the third set of linear-shaped conductive structures is manufactured separately from both the first and second sets of linear-shaped conductive structures. 13. A semiconductor chip as recited in claim 12, wherein the integer multiple of the fixed pitch is equal to the fixed pitch multiplied by a whole number selected from a set of whole numbers including zero. 14. A semiconductor chip as recited in claim 13, wherein some of plurality of linear-shaped conductive structures are substantially co-aligned such that the distance as measured in the second direction perpendicular to the first direction between their first-direction-oriented-lengthwise-centerlines is substantially equal to zero. 15. A semiconductor chip as recited in claim 12, wherein a spacing between at least one of the linear-shaped conductive structures of the first set of linear-shaped conductive structures and an adjacent one of the linear-shaped conductive structures of the second set of linear-shaped conductive structures is outside a fabrication capability of a semiconductor fabrication process. 16. A semiconductor chip as recited in claim 15, wherein a spacing between at least one of the linear-shaped conductive structures of the first set of linear-shaped conductive structures and an adjacent one of the linear-shaped conductive structures of the third set of linear-shaped conductive structures is outside a fabrication capability of a semiconductor fabrication process. 17. A semiconductor chip as recited in claim 16, wherein a spacing between at least one of the linear-shaped conductive structures of the second set of linear-shaped conductive structures and an adjacent one of the linear-shaped conductive structures of the third set of linear-shaped conductive structures is outside a fabrication capability of a semiconductor fabrication process. 18. A semiconductor chip as recited in claim 12, wherein the first set of linear-shaped conductive structures correspond to a first plurality of linear-shaped conductive structures, and wherein the second set of linear-shaped conductive structures correspond to a second plurality of linear-shaped conductive structures, andwherein the third set of linear-shaped conductive structures correspond to a third plurality of linear-shaped conductive structures, andwherein the fixed pitch of the gate electrode level corresponds to a first pitch, andwherein the semiconductor chip further comprises a first interconnect level including a fourth plurality of linear-shaped conductive structures defined to extend lengthwise in the first direction, the fourth plurality of linear-shaped conductive structures positioned in accordance with a second pitch such that a distance as measured in the second direction perpendicular to the first direction between first-direction-oriented-lengthwise-centerlines of any two of the fourth plurality of linear-shaped conductive structures is substantially equal to an integer multiple of the second pitch,the first interconnect level including a fifth plurality of linear-shaped conductive structures defined to extend lengthwise in the first direction, the fifth plurality of linear-shaped conductive structures positioned in accordance with a third pitch such that a distance as measured in the second direction perpendicular to the first direction between first-direction-oriented-lengthwise-centerlines of any two of the fifth plurality of linear-shaped conductive structures is substantially equal to an integer multiple of the third pitch. 19. A semiconductor chip as recited in claim 18, wherein at least one of the second and third pitches is equal to the first pitch. 20. A semiconductor chip as recited in claim 18, wherein at least one of the second and third pitches is equal to the first pitch multiplied by a ratio of integers. 21. A semiconductor chip as recited in claim 12, wherein each of the plurality of linear-shaped conductive structures has a total length as measured in the first direction along its first-direction-oriented-lengthwise-centerline, and wherein the total length of each linear-shaped conductive structure of the first set of linear-shaped conductive structures is equal. 22. A semiconductor chip as recited in claim 21, wherein the second set of linear-shaped conductive structures includes linear-shaped conductive structures of different total length. 23. A semiconductor chip as recited in claim 22, wherein the third set of linear-shaped conductive structures includes linear-shaped conductive structures of different total length. 24. A semiconductor chip as recited in claim 12, wherein some linear-shaped conductive structures of the second set of linear-shaped conductive structures are co-aligned such that the distance as measured in the second direction perpendicular to the first direction between their first-direction-oriented-lengthwise-centerlines is equal to zero, and wherein adjacently positioned co-aligned linear-shaped conductive structures of the second set of linear-shaped conductive structures are separated from each other by a uniform end-to-end spacing as measured in the first direction. 25. A semiconductor chip as recited in claim 24, wherein some linear-shaped conductive structures of the third set of linear-shaped conductive structures are co-aligned such that the distance as measured in the second direction perpendicular to the first direction between their first-direction-oriented-lengthwise-centerlines is equal to zero, and wherein adjacently positioned co-aligned linear-shaped conductive structures of the third set of linear-shaped conductive structures are separated from each other by the uniform end-to-end spacing as measured in the first direction.
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