Dynamic low-latency processing circuits using interleaving
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H03M-001/00
H04B-001/10
H04H-040/18
H03M-013/27
출원번호
US-0729791
(2017-10-11)
등록번호
US-10135475
(2018-11-20)
발명자
/ 주소
Ray, Gary A.
출원인 / 주소
The Boeing Company
대리인 / 주소
Ostrager Chong Flaherty & Broitman P.C.
인용정보
피인용 횟수 :
0인용 특허 :
6
초록▼
Systems and methods for processing a multitude of variable and varying signals in real time with low latency using fixed hardware with fixed processing resources, such as those within an application-specific integrated circuit (ASIC) or a field-programmable gated array (FPGA). The signal processing
Systems and methods for processing a multitude of variable and varying signals in real time with low latency using fixed hardware with fixed processing resources, such as those within an application-specific integrated circuit (ASIC) or a field-programmable gated array (FPGA). The signal processing systems and methods allow the resource allocation to continuously adjust their processing as a result of changing signal conditions. In accordance with various embodiments, fixed processing resources in ASIC or FPGA form are dynamically allocated through an intelligent interleaving methodology that efficiently maps the signal processing of incoming signals while essentially preserving the same latency as if each signal channel were processed at the full sample rate. This is accomplished by multiplexing under the control of a resource sharing algorithm.
대표청구항▼
1. A method for processing signals that vary in bandwidth using a set of fixed hardware resources, the method comprising: (a) sampling a received signal having a frequency within a specified bandwidth to produce signal samples;(b) generating signal information representing characteristics of the rec
1. A method for processing signals that vary in bandwidth using a set of fixed hardware resources, the method comprising: (a) sampling a received signal having a frequency within a specified bandwidth to produce signal samples;(b) generating signal information representing characteristics of the received signals, including estimated bandwidth of the received signals;(c) mapping signal processing of the received signal samples onto a fixed set of processing circuitry in accordance with an interleaving scheme, wherein the mapping is dynamically changed by a dynamic interleaving controller as the characteristics of the received signals change;(d) interleaving signal processing of the received signal samples by the processing circuitry in accordance with the mapping;(e) generating information vectors comprising respective data sets of parameter values of received signals; and(f) storing the data sets of parameter values of the information vectors in a non-transitory tangible computer-readable storage medium. 2. The method as recited in claim 1, further comprising: identifying a signal emitter based on the stored data sets of parameter values;locating the signal emitter; andsending control signals to an actuator controller of a vehicle, which control signals direct a movement of the vehicle based on a location of the signal emitter. 3. The method as recited in claim 1, wherein the mapping maps virtual channel numbers to respective circuits of the processing circuitry. 4. The method as recited in claim 3, wherein step (c) comprises using the signal information to look up in a circuit/algorithm table a circuit or sequence of circuits of the processing circuitry designed to process signal samples of a type based on the signal information. 5. The method as recited in claim 4, wherein step (c) further comprises sending a virtual channel request to a multiplicity of dynamic input/output interleavers, which request includes data representing the estimated bandwidth of the received signals. 6. The method as recited in claim 5, wherein step (c) further comprises determining in each dynamic input/output interleaver whether an empty slot exists for a compatible interleaving period that meets bandwidth requirements or not. 7. The method as recited in claim 6, wherein determining whether an empty slot exists comprises finding empty slots in a respective interleaving buffer in each dynamic input/output interleaver, wherein the interleaving buffer stores data identifying an input channel, an output channel, a period, a virtual channel and a circuit of the processing circuitry associated with each dynamic input/output interleaver. 8. The method as recited in claim 7, wherein step (c) further comprises selecting from any dynamic input/output interleavers that have an empty slot a dynamic input/output interleaver with a smallest latency. 9. The method as recited in claim 7, wherein step (d) comprises setting up an interleaving buffer in a dynamic input/output interleaver and interleaving data with an associated virtual channel number as input to an associated circuit of the processing circuitry. 10. The method as recited in claim 3, wherein samples proceed through a circuit of the processing circuitry in a pipelined fashion, wherein the pipeline comprises only samples associated with the virtual channel that the circuit is part of. 11. The method as recited in claim 9, wherein the processing circuitry produces a signal when current virtual channel processing is complete. 12. The method as recited in claim 11, wherein step (e) comprises formatting an output vector that concatenates output from the dynamic input/output interleavers and the signal information representing characteristics of the received signals to form an information vector. 13. The method as recited in claim 12, wherein the information vector comprises data representing a pulse descriptor word. 14. A system for processing signals that vary in bandwidth, comprising: a transducer for converting received energy waves into a received signal in electrical form;a filter for passing a portion of the received signal having a frequency within a selected frequency bandwidth;a sampler comprising hardware or firmware configured to sample the received signal output by the filter to produce signal samples;a multiplicity of physical processing units, each physical processing unit comprising a respective multiplicity of processing circuits configured to process signal samples in a pipelined manner and each physical processing unit being configured to process signal samples in accordance with a respective algorithm;a multiplicity of dynamic input/output interleavers, each dynamic input/output interleaver having an output line connected to an input line of a respective physical processing unit;a dynamic interleaving controller communicatively coupled to each dynamic input/output interleaver of the multiplicity of dynamic input/output interleavers and configured to receive signal information representing characteristics of received signals, including estimated bandwidth of the received signals, and to cause a virtual processing channel to be started on a physical processing unit in accordance with a mapping between a virtual channel number and a processing circuit based on that signal information;an input channel block communicatively coupled to each dynamic input/output interleaver of the multiplicity of dynamic input/output interleavers and to each physical processing unit of the multiplicity of physical processing units;an output channel block communicatively coupled to each dynamic input/output interleaver of the multiplicity of dynamic input/output interleavers and to the dynamic interleaving controller; anda clock that outputs clock signals to the multiplicity of physical processing units, the multiplicity of dynamic input/output interleavers, the dynamic interleaving controller, the input channel block and the output channel block. 15. The system as recited in claim 14, wherein the dynamic interleaving controller is configured to: use the signal information to look up in a circuit/algorithm table a processing circuit configured to process signal samples of a type characterized by the signal information; andsend a virtual channel request to the multiplicity of dynamic input/output interleavers, which request includes data representing the estimated bandwidth of the received signals. 16. The system as recited in claim 15, wherein each dynamic input/output interleaver comprises an interleaving buffer and is configured to determine whether an empty slot exists in the interleaving buffer for a compatible interleaving period that meets bandwidth requirements or not and then send a message to the dynamic interleaving controller containing information representing a result of that determination. 17. The system as recited in claim 16, wherein the dynamic interleaving controller is further configured to select from any dynamic input/output interleavers that have an empty slot a dynamic input/output interleaver with a smallest latency. 18. The system as recited in claim 16, wherein each dynamic input/output interleaver is configured to set up its interleaving buffer and then interleave data with an associated virtual channel number as input to an associated physical processing unit. 19. The system as recited in claim 14, wherein the output channel block is configured to format an output vector that concatenates output from the dynamic input/output interleavers and the signal information representing characteristics of the received signals from the dynamic interleaving controller to form an information vector. 20. A system for processing signals that vary in bandwidth using dynamic interleaving, comprising: a multiplicity of physical processing units, each physical processing unit comprising a respective multiplicity of processing circuits configured to process signal samples in a pipelined manner and each physical processing unit being configured to process signal samples in accordance with a respective algorithm;a multiplicity of dynamic input/output interleavers, each dynamic input/output interleaver having an output line connected to an input line of a respective physical processing unit;a dynamic interleaving controller communicatively coupled to each dynamic input/output interleaver of the multiplicity of dynamic input/output interleavers and configured to receive signal information representing characteristics of received signals, including estimated bandwidth of the received signals, and to cause a virtual processing channel to be started on one or more physical processing units in accordance with a dynamic resource sharing algorithm that dynamically adjusts the interleaving sequence as new signal processing by newly received signals;an input channel block communicatively coupled to each dynamic input/output interleaver of the multiplicity of dynamic input/output interleavers and to each physical processing unit of the multiplicity of physical processing units;an output channel block communicatively coupled to each dynamic input/output interleaver of the multiplicity of dynamic input/output interleavers and to the dynamic interleaving controller; anda clock that outputs clock signals to the multiplicity of physical processing units, the multiplicity of dynamic input/output interleavers, the dynamic interleaving controller, the input channel block and the output channel block. 21. The system as recited in claim 20, wherein: the dynamic interleaving controller is configured to use the signal information to look up in a circuit/algorithm table a processing circuit configured to process signal samples of a type characterized by the signal information, and send a virtual channel request to the multiplicity of dynamic input/output interleavers, which request includes data representing the estimated bandwidth of the received signals;each dynamic input/output interleaver comprises an interleaving buffer and is configured to determine whether an empty slot exists in the interleaving buffer for a compatible interleaving period that meets bandwidth requirements or not and then send a message to the dynamic interleaving controller containing information representing a result of that determination; andthe dynamic interleaving controller is further configured to select from any dynamic input/output interleavers that have an empty slot a dynamic input/output interleaver with a smallest latency. 22. The system as recited in claim 20, wherein the output channel block is configured to format an output vector that concatenates output from the dynamic input/output interleavers and the signal information representing characteristics of the received signals from the dynamic interleaving controller to form an information vector.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (6)
Hoyos,Sebastian; Sadler,Brian M; Arce,Gonzalo R., Analog to digital conversion with signal expansion.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.