최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0696651 (2017-09-06) |
등록번호 | US-10141335 (2018-11-27) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 0 인용 특허 : 580 |
Gate structures formed from substantially rectangular shaped gate structure layout shapes positioned on a gate horizontal grid having at least seven gate gridlines within a region. A first-metal layer including first-metal structures formed from substantially rectangular shaped first-metal structure
Gate structures formed from substantially rectangular shaped gate structure layout shapes positioned on a gate horizontal grid having at least seven gate gridlines within a region. A first-metal layer including first-metal structures formed from substantially rectangular shaped first-metal structure layout shapes is formed above top surfaces of the gate structures within the region. The first-metal structure layout shapes are positioned on a first-metal vertical grid having at least eight first-metal gridlines. At least six contact structures are formed from substantially rectangular shaped contact structure layout shapes in physical and electrical contact with corresponding ones of at least six of the gate structures. A total number of first-transistor-type-only gate structures equals a total number of second-transistor-type-only gate structures within the region. At least four transistors of a first transistor type and at least four transistors of a second transistor type collectively form part of a logic circuit within the region.
1. A semiconductor chip, comprising: gate structures formed within a region of the semiconductor chip, the gate structures formed in part based on corresponding gate structure layout shapes used as an input to a lithography process, the gate structure layout shapes positioned in accordance with a ga
1. A semiconductor chip, comprising: gate structures formed within a region of the semiconductor chip, the gate structures formed in part based on corresponding gate structure layout shapes used as an input to a lithography process, the gate structure layout shapes positioned in accordance with a gate horizontal grid, the gate horizontal grid including at least seven gate gridlines, each gate structure layout shape having a substantially rectangular shape and positioned to extend lengthwise in a y-direction in a substantially centered manner along an associated gate gridline, each gate gridline having at least one gate structure layout shape positioned thereon, wherein adjacently positioned ones of the gate structures are separated from each other by a gate pitch of less than or equal to about 193 nanometers, each of the gate structures having a width of less than or equal to about 45 nanometers, wherein each pair of the gate structures that are positioned in and end-to-end manner are separated from each other by a line end-to-line end gap of less than or equal to about 193 nanometers;a first-metal layer formed above top surfaces of the gate structures within the region of the semiconductor chip, the first-metal layer positioned first in a stack of metal layers counting upward from top surfaces of the gate structures, the first-metal layer separated from the top surfaces of the gate structures by at least one insulator material, adjacent metal layers in the stack of metal layers separated by at least one insulator material, wherein the first-metal layer includes first-metal structures formed in part based on corresponding first-metal structure layout shapes used as an input to a lithography process, the first-metal structure layout shapes positioned in accordance with a first-metal vertical grid, the first-metal vertical grid including at least eight first-metal gridlines, each first-metal structure layout shape having a substantially rectangular shape and positioned to extend lengthwise in an x-direction in a substantially centered manner on an associated first-metal gridline, each of the first-metal structures having at least one adjacent first-metal structure positioned next to each of its sides at a y-coordinate spacing of less than or equal to 193 nanometers, wherein each pair of the first-metal structures that are positioned in an end-to-end manner are separated by a line end-to-line end gap of less than or equal to about 193 nanometers;at least six contact structures formed within the region of the semiconductor chip, the at least six contact structures formed in part utilizing corresponding at least six contact structure layout shapes as an input to a lithography process, the at least six contact structures formed in physical and electrical contact with corresponding ones of at least six of the gate structures, each of the at least six contact structure layout shapes having a substantially rectangular shape and a corresponding length greater than a corresponding width and with the corresponding length oriented in the x-direction, each of the at least six contact structure layout shapes positioned and sized to form its corresponding contact structure to overlap both edges of the top surface of the gate structure to which it is in physical and electrical contact,wherein at least one gate structure within the region is a first-transistor-type-only gate structure that forms at least one gate electrode of at least one transistor of a first transistor type and does not form a gate electrode of a transistor of a second transistor type, wherein at least one gate structure within the region is a second-transistor-type-only gate structure that forms at least one gate electrode of at least one transistor of the second transistor type and does not form a gate electrode of a transistor of the first transistor type, wherein a total number of first-transistor-type-only gate structures within the region is equal to a total number of second-transistor-type-only gate structures within the region, wherein the region includes at least four transistors of the first transistor type and at least four transistors of the second transistor type that collectively form part of a logic circuit. 2. The semiconductor chip as recited in claim 1, wherein the region includes a second-metal layer including second-metal structures formed in part based on corresponding second-metal structure layout shapes used as an input to a lithography process, the second-metal structure layout shapes positioned in accordance with a second-metal horizontal grid, the second-metal horizontal grid including at least eight second-metal gridlines, each second-metal structure layout shape in the region having a substantially rectangular shape and positioned to extend lengthwise in the y-direction in a substantially centered manner along an associated second-metal gridline, wherein at least eight of the at least eight second-metal gridlines have at least one second-metal structure layout shape positioned thereon, wherein each of the second-metal structures has at least one adjacent second-metal structure positioned next to each of its sides at an x-coordinate spacing of less than or equal to 193 nanometers, wherein each pair of the second-metal structures that are positioned in an end-to-end manner are separated by a line end-to-line end gap, wherein the second-metal layer is positioned second in the stack of metal layers counting upward from the top surfaces of the gate structures. 3. The semiconductor chip as recited in claim 2, wherein each first-metal structure layout shape in the region has a width measured in the y-direction that is either a first width or a second width different than the first width. 4. The semiconductor chip as recited in claim 3, wherein at least one gate structure within the region that forms at least one gate electrode of at least one transistor of a first transistor type and does not form a gate electrode of a transistor of a second transistor type is electrically connected to at least one gate structure within the region that forms at least one gate electrode of at least one transistor of the second transistor type and does not form a gate electrode of a transistor of the first transistor type through an electrical connection that includes at least one first-metal structure and at least one second-metal structure. 5. The semiconductor chip as recited in claim 2, wherein the at least six contact structure layout shapes are positioned in accordance with a contact vertical grid, the contact vertical grid including contact gridlines extending in the x-direction, each of the at least six contact structure layout shapes positioned to extend lengthwise in the x-direction in a substantially centered manner along an associated contact gridline, and at least two of the at least six contact structure layout shapes positioned to also extend lengthwise in the x-direction in a substantially centered manner along an associated first-metal gridline. 6. The semiconductor chip as recited in claim 2, wherein each second-metal structure layout shape in the region is positioned next to at least one other second-metal structure layout shape on a first side in accordance with a second-metal pitch and is positioned next to at least one other second-metal structure layout shape on a second side in accordance with the second-metal pitch, wherein the second-metal pitch is measured in the x-direction and is equal to the gate pitch. 7. The semiconductor chip as recited in claim 6, wherein each second-metal structure layout shape in the region has a substantially equal width as measured in the x-direction. 8. The semiconductor chip as recited in claim 7, wherein each first-metal structure layout shape in the region has a width measured in the y-direction that is either a first width or a second width different than the first width. 9. The semiconductor chip as recited in claim 7, wherein the region has a size of 1930 nanometers as measured in the x-direction and a size of 1930 nanometers as measured in the y-direction. 10. The semiconductor chip as recited in claim 7, wherein the region includes a third-metal layer including third-metal structures formed in part based on corresponding third-metal structure layout shapes used as an input to a lithography process, the third-metal structure layout shapes positioned in accordance with a third-metal vertical grid, the third-metal vertical grid including at least eight third-metal gridlines, each third-metal structure layout shape in the region having a substantially rectangular shape and positioned to extend lengthwise in the x-direction in a substantially centered manner along an associated third-metal gridline, wherein at least eight of the at least eight third-metal gridlines have at least one third-metal structure layout shape positioned thereon, wherein each third-metal structure in the region has at least one adjacent third-metal structure positioned next to each of its sides at a y-coordinate spacing of less than or equal to 193 nanometers, wherein each pair of the third-metal structures that are positioned in an end-to-end manner are separated by a line end-to-line end gap, wherein the third-metal layer is positioned third in the stack of metal layers counting upward from the top surfaces of the gate structures. 11. The semiconductor chip as recited in claim 10, wherein each second-metal structure layout shape in the region is positioned next to at least one other second-metal structure layout shape on a first side in accordance with a second-metal pitch and is positioned next to at least one other second-metal structure layout shape on a second side in accordance with the second-metal pitch, wherein the second-metal pitch is measured in the x-direction and is equal to the gate pitch. 12. The semiconductor chip as recited in claim 10, wherein the region includes a fourth-metal layer including fourth-metal structures formed in part based on corresponding fourth-metal structure layout shapes used as an input to a lithography process, the fourth-metal structure layout shapes positioned in accordance with a fourth-metal horizontal grid, the fourth-metal horizontal grid including at least eight fourth-metal gridlines, each fourth-metal structure layout shape in the region having a substantially rectangular shape and positioned to extend lengthwise in the y-direction in a substantially centered manner along an associated fourth-metal gridline, wherein at least eight of the at least eight fourth-metal gridlines have at least one fourth-metal structure layout shape positioned thereon, wherein each fourth-metal structure in the region has at least one adjacent fourth-metal structure positioned next to each of its sides at an x-coordinate spacing of less than or equal to 193 nanometers, wherein each pair of the fourth-metal structures that are positioned in an end-to-end manner are separated by a line end-to-line end gap, wherein the fourth-metal layer is positioned fourth in the stack of metal layers counting upward from the top surfaces of the gate structures. 13. The semiconductor chip as recited in claim 2, wherein each first-metal structure layout shape in the region is positioned next to at least one other first-metal structure layout shape on a first side in accordance with a first-metal pitch and is positioned next to at least one other first-metal structure layout shape on a second side in accordance with the first-metal pitch. 14. The semiconductor chip as recited in claim 13, wherein the region has a size of 1930 nanometers as measured in the x-direction and a size of 1930 nanometers as measured in the y-direction. 15. The semiconductor chip as recited in claim 1, wherein each transistor within the region of the semiconductor chip is formed in part by a corresponding diffusion region, wherein each diffusion region that forms part of at least one transistor within the region of the semiconductor chip has a substantially rectangular shape. 16. The semiconductor chip as recited in claim 1, wherein the at least four transistors of the first transistor type and the at least four transistors of the second transistor type within the region collectively form part of an inverting two-to-one multiplexer. 17. The semiconductor chip as recited in claim 1, wherein at least one of the at least six contact structures is in physical and electrical contact with, and is substantially centered in the x-direction on, a gate structure within the region that forms at least one gate electrode of at least one transistor of the first transistor type and that does not form a gate electrode of a transistor of the second transistor type. 18. The semiconductor chip as recited in claim 1, wherein each of at least four of the first-metal gridlines has at least two first-metal structure layout shapes positioned thereon within the region, wherein each of the at least two first-metal structure layout shapes is positioned next to and spaced apart from at least one other first-metal structure layout shape in accordance with a fixed pitch. 19. The semiconductor chip as recited in claim 1, wherein any first-metal structure layout shape positioned on any first-metal gridline within the region is positioned next to and spaced apart from at least one other first-metal structure layout shape in accordance with a fixed pitch. 20. The semiconductor chip as recited in claim 1, wherein the region includes a second-metal layer including second-metal structures formed in part based on corresponding second-metal structure layout shapes used as an input to a lithography process, the second-metal structure layout shapes positioned in accordance with a second-metal horizontal grid, the second-metal horizontal grid including at least eight second-metal gridlines, each second-metal structure layout shape in the region having a substantially rectangular shape and positioned to extend lengthwise in the y-direction in a substantially centered manner along an associated second-metal gridline, wherein at least eight of the at least eight second-metal gridlines have at least one second-metal structure layout shape positioned thereon, wherein each second-metal structure in the region has at least one adjacent second-metal structure positioned next to each of its sides at an x-coordinate spacing of less than or equal to 193 nanometers, wherein each pair of the second-metal structures that are positioned in an end-to-end manner are separated by a line end-to-line end gap, wherein the second-metal layer is positioned second in the stack of metal layers counting upward from the top surfaces of the gate structures, wherein the region includes a third-metal layer including third-metal structures formed in part based on corresponding third-metal structure layout shapes used as an input to a lithography process, the third-metal structure layout shapes positioned in accordance with a third-metal vertical grid, the third-metal vertical grid including at least eight third-metal gridlines, each third-metal structure layout shape in the third-metal layer having a substantially rectangular shape and positioned to extend lengthwise in the x-direction in a substantially centered manner along an associated third-metal gridline, wherein at least eight of the at least eight third-metal gridlines have at least one third-metal structure layout shape positioned thereon, wherein each third-metal structure in the region has at least one adjacent third-metal structure positioned next to each of its sides at a y-coordinate spacing of less than or equal to 193 nanometers, wherein each pair of the third-metal structures that are positioned in an end-to-end manner are separated by a line end-to-line end gap, wherein the third-metal layer is positioned third in the stack of metal layers counting upward from the top surfaces of the gate structures. 21. The semiconductor chip as recited in claim 20, wherein the region includes a fourth-metal layer including fourth-metal structures formed in part based on corresponding fourth-metal structure layout shapes used as an input to a lithography process, the fourth-metal structure layout shapes positioned in accordance with a fourth-metal horizontal grid, the fourth-metal horizontal grid including at least eight fourth-metal gridlines, each fourth-metal structure layout shape in the region having a substantially rectangular shape and positioned to extend lengthwise in the y-direction in a substantially centered manner along an associated fourth-metal gridline, wherein at least eight of the at least eight fourth-metal gridlines have at least one fourth-metal structure layout shape positioned thereon, wherein each fourth-metal structure in the region has at least one adjacent fourth-metal structure positioned next to each of its sides at an x-coordinate spacing of less than or equal to 193 nanometers, wherein each pair of the fourth-metal structures that are positioned in an end-to-end manner are separated by a line end-to-line end gap, wherein the fourth-metal layer is positioned fourth in the stack of metal layers counting upward from the top surfaces of the gate structures. 22. The semiconductor chip as recited in claim 20, wherein the at least four transistors of the first transistor type include a first transistor of the first transistor type, wherein the at least four transistors of the second transistor type include a first transistor of the second transistor type, wherein a gate structure that forms a gate electrode of the first transistor of the first transistor type and a gate structure that forms a gate electrode of the first transistor of the second transistor type are formed to extend lengthwise along a same line, wherein no other transistor is positioned on the same line between the gate structures that form the gate electrodes of the first transistor of the first transistor type and the first transistor of the second transistor type, wherein each transistor within the region of the semiconductor chip is formed in part by a corresponding diffusion region, wherein a diffusion region of the first transistor of the first transistor type is electrically connected to a diffusion region of the first transistor of the second transistor type,wherein the at least six contact structures include a contact structure substantially centered in the x-direction on the same line at a location between the diffusion regions of the first transistor of the first transistor type and the first transistor of the second transistor type. 23. The semiconductor chip as recited in claim 22, wherein an electrical connection between the diffusion region of the first transistor of the first transistor type and the diffusion region of the first transistor of the second transistor type includes at least one first-metal structure and at least one second-metal structure. 24. The semiconductor chip as recited in claim 23, wherein the gate electrode of the first transistor of the first transistor type is electrically connected to the gate electrode of the first transistor of the second transistor type. 25. The semiconductor chip as recited in claim 1, wherein the at least four transistors of the first transistor type include a first transistor of the first transistor type, wherein the at least four transistors of the second transistor type include a first transistor of the second transistor type, wherein a gate structure that forms a gate electrode of the first transistor of the first transistor type and a gate structure that forms a gate electrode of the first transistor of the second transistor type are formed to extend lengthwise along a same line, wherein no other transistor is positioned on the same line between the gate structures that form the gate electrodes of the first transistor of the first transistor type and the first transistor of the second transistor type, wherein each transistor within the region of the semiconductor chip is formed in part by a corresponding diffusion region, wherein a diffusion region of the first transistor of the first transistor type is electrically connected to a diffusion region of the first transistor of the second transistor type,wherein the at least six contact structures include a contact structure substantially centered in the x-direction on the same line at a location between the diffusion regions of the first transistor of the first transistor type and the first transistor of the second transistor type. 26. The semiconductor chip as recited in claim 25, wherein an electrical connection between the diffusion region of the first transistor of the first transistor type and the diffusion region of the first transistor of the second transistor type includes at least one first-metal structure and at least one second-metal structure in a second-metal layer within the region, wherein the second-metal layer includes second-metal structures formed in part based on corresponding second-metal structure layout shapes used as an input to a lithography process, the second-metal structure layout shapes positioned in accordance with a second-metal horizontal grid, the second-metal horizontal grid including at least eight second-metal gridlines, each second-metal structure layout shape in the region having a substantially rectangular shape and positioned to extend lengthwise in the y-direction in a substantially centered manner along an associated second-metal gridline, wherein at least eight of the at least eight second-metal gridlines have at least one second-metal structure layout shape positioned thereon, wherein each second-metal structure in the region has at least one adjacent second-metal structure positioned next to each of its sides at an x-coordinate spacing of less than or equal to 193 nanometers, wherein each pair of the second-metal structures that are positioned in an end-to-end manner are separated by a line end-to-line end gap, wherein the second-metal layer is positioned second in the stack of metal layers formed above the gate structures counting upward from the top surfaces of the gate structures. 27. The semiconductor chip as recited in claim 1, wherein the at least four transistors of the first transistor type are collectively separated from the at least four transistors of the second transistor type by an inner region that does not include another transistor. 28. The semiconductor chip as recited in claim 27, wherein at least one of the at least six contact structures is in physical and electrical contact with, and is substantially centered in the x-direction on, a given gate structure within the region that forms at least one gate electrode of at least one transistor, wherein the at least one of the at least six contact structures is positioned over the inner region. 29. A semiconductor chip, comprising: gate structures formed within a region of the semiconductor chip, the gate structures formed in part based on corresponding gate structure layout shapes used as an input to a lithography process, the gate structure layout shapes positioned in accordance with a gate horizontal grid that includes at least seven gate gridlines, each gate structure layout shape having a substantially rectangular shape and positioned to extend lengthwise in a y-direction in a substantially centered manner along an associated gate gridline, each gate gridline having at least one gate structure layout shape positioned thereon, wherein adjacently positioned ones of the gate structures are separated from each other by a gate pitch of less than or equal to about 193 nanometers, each of the gate structures having a width of less than or equal to about 45 nanometers, wherein each pair of the gate structures that are positioned in an end-to-end manner are separated from each other by a line end-to-line end gap of less than or equal to about 193 nanometers, wherein at least one gate structure within the region is a first-transistor-type-only gate structure that forms at least one gate electrode of at least one transistor of a first transistor type and does not form a gate electrode of a transistor of a second transistor type, wherein at least one gate structure within the region is a second-transistor-type-only gate structure that forms at least one gate electrode of at least one transistor of the second transistor type and does not form a gate electrode of a transistor of the first transistor type, wherein a total number of first-transistor-type-only gate structures within the region is equal to a total number of second-transistor-type-only gate structures within the region,wherein each gate structure that forms any transistor gate electrode within the region has a respective top surface in physical and electrical contact with a corresponding contact structure formed in part based on a corresponding contact structure layout shape having a substantially rectangular shape, wherein each contact structure that contacts a given gate structure that forms any transistor gate electrode does not contact another gate structure, wherein each contact structure layout shape has a corresponding length greater than or equal to a corresponding width and is oriented to have its corresponding length extend in an x-direction, wherein each contact structure that contacts a corresponding gate structure has its corresponding contact structure layout shape positioned to overlap at least one edge of the gate structure layout shape of the corresponding gate structure,wherein the region includes at least four transistors of the first transistor type and at least four transistors of the second transistor type that collectively form a portion of a multiplexer or a portion of a latch, wherein at least one first-transistor-type-only gate structure within the region is included within the portion of the multiplexer or the portion of the latch, wherein at least one second-transistor-type-only gate structure within the region is included within the portion of the multiplexer or the portion of the latch. 30. A semiconductor chip, comprising: gate structures formed within a region of the semiconductor chip, the gate structures formed in part based on corresponding gate structure layout shapes used as an input to a lithography process, the gate structure layout shapes positioned in accordance with a gate horizontal grid that includes a number of gate gridlines, each gate structure layout shape having a substantially rectangular shape and positioned to extend lengthwise in a y-direction in a substantially centered manner along an associated gate gridline, each gate gridline having at least one gate structure layout shape positioned thereon, wherein adjacently positioned ones of the gate structures are separated from each other by a gate pitch of less than or equal to about 193 nanometers, each of the gate structures having a width of less than or equal to about 45 nanometers, wherein each pair of the gate structures that are positioned in an end-to-end manner are separated from each other by a line end-to-line end gap of less than or equal to about 193 nanometers, wherein at least one gate structure within the region is a first-transistor-type-only gate structure that forms at least one gate electrode of at least one transistor of a first transistor type and does not form a gate electrode of a transistor of a second transistor type, wherein at least one gate structure within the region is a second-transistor-type-only gate structure that forms at least one gate electrode of at least one transistor of the second transistor type and does not form a gate electrode of a transistor of the first transistor type, wherein a total number of first-transistor-type-only gate structures within the region is equal to a total number of second-transistor-type-only gate structures within the region,wherein each of at least six gate structures within the region has a respective top surface in physical and electrical contact with a corresponding at least six contact structures that are formed in part based on corresponding contact structure layout shapes having a substantially rectangular shape, wherein each of the at least six contact structures is in physical contact with only one corresponding gate structure, wherein each contact structure layout shape of the at least six contact structures is centered in an x-direction on the gate structure layout shape of the gate structure with which it physical contacts, wherein each contact structure layout shape of the at least six contact structures has a corresponding length greater than or equal to a corresponding width and is oriented to have its corresponding length extend in an x-direction, wherein each contact structure of the at least six contact structures has its contact structure layout shape positioned to overlap at least one edge of the gate structure layout shape of the gate structure that is contacted by the contact structure,wherein the region includes at least four transistors of the first transistor type and at least four transistors of the second transistor type that collectively form a portion of a multiplexer or a portion of a latch, wherein at least one first-transistor-type-only gate structure within the region is included within the portion of the multiplexer or the portion of the latch, wherein at least one second-transistor-type-only gate structure within the region is included within the portion of the multiplexer or the portion of the latch.
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