Systems and methods for managing public and private queues for a storage system
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-003/06
G06F-013/14
G06F-013/12
G06F-009/52
G06F-013/38
출원번호
US-0509476
(2014-10-27)
등록번호
US-10162571
(2018-12-25)
국제출원번호
PCT/JP2014/078497
(2014-10-27)
국제공개번호
WO2016/067339
(2016-05-06)
발명자
/ 주소
Takada, Aritoki
출원인 / 주소
HITACHI, LTD.
대리인 / 주소
Procopio, Cory, Hargreaves & Savitch LLP
인용정보
피인용 횟수 :
0인용 특허 :
11
초록▼
A storage system includes: a controller including a plurality of processors; an interface device; and a plurality of queues associated with the interface device. The plurality of queues each store data transmitted from a processor allocated to the queue to the interface device. The plurality of queu
A storage system includes: a controller including a plurality of processors; an interface device; and a plurality of queues associated with the interface device. The plurality of queues each store data transmitted from a processor allocated to the queue to the interface device. The plurality of queues include a private queue and a public queue. The private queue is a queue allocated with only a first processor as one of the plurality of processors, the private queue requiring no exclusion processing when data is stored, whereas the public queue is a queue allocated with two or more second processors in the plurality of processors, the public queue requiring the exclusion processing when data is stored.
대표청구항▼
1. A storage system comprising: a controller configured to include a plurality of processors;an interface device to which a storage device is coupled; anda plurality of queues associated with the interface device, the queues being configured to include a private queue and a public queue,each of the
1. A storage system comprising: a controller configured to include a plurality of processors;an interface device to which a storage device is coupled; anda plurality of queues associated with the interface device, the queues being configured to include a private queue and a public queue,each of the plurality of queues being configured to store data transmitted from a processor allocated to the queue to the interface device, and each of the plurality of queues being configured to transmit the data to the interface device,the private queue being a queue allocated with only a single processor from the plurality of processors, and wherein exclusion processing is not conducted when data is stored in the private queue,the public queue being a queue allocated with multiple ones of the plurality of processors other than the single processor, and wherein the exclusion processing is conducted when data is stored in the public queue, andthe controller is configured to,in a case where allocation switching between the single processor allocated to the private queue and one of the multiple ones of the plurality of processors allocated to the public queue is executed and a public frequency for which data is stored in the public queue is smaller than before the allocation switching by a predetermined threshold value or more, execute the allocation switching. 2. The storage system according to claim 1, wherein the controller is configured to determine the single processor to be allocated to the private queue, based on a plurality of data issuing frequencies of data issuing respectively from the plurality of processors to the interface device. 3. The storage system according to claim 1, wherein data is issued due to the plurality of processors each executing a process, andthe controller is configured to execute, when a predetermined condition related to a public frequency indicating a frequency of data storage to the public queue and to a load of the single processor is satisfied, process moving in which a process executed by a target processor from the multiple ones of the plurality of processors is moved to the single processor. 4. The storage system according to claim 3, wherein the predetermined condition is a condition in which an estimated public frequency is smaller than a current public frequency by a predetermined threshold value or more, and the load of the first processor is smaller than a predetermined threshold value,the estimated public frequency is a public frequency configured for a hypothetical case where the process moving in which the process executed by the target processor is moved to the single processor is executed, andthe current public frequency is a public frequency before the process moving. 5. A storage system, comprising: a controller configured to include a plurality of processors; an interface device to which a storage device is coupled, anda plurality of queues associated with the interface device, the queues being configured toeach of the plurality of queues being configured to store data transmitted from a processor allocated to the queue to the interface device, and each of the plurality of queues being configured to transmit the data to the interface device;wherein the controller is configured tomanage a queue type, which is either private or public, of each of the plurality of queues, andstore data in the public queue after executing, on the public queue, exclusion processing involving locking the queue, and store data in the private queue without executing the exclusion processing,the controller is configured to repeatedly update allocation relationship between the plurality of processors and the plurality of queues, andthe controller is configured to change, for a queue having the number of allocated processors decreased to one, the queue type from the public to the private. 6. The storage system according to claim 5, wherein the controller is configured to determine, for a first queue which is one of the plurality of queues with a largest use load index, whether to change the queue type from the public to the private, andthe use load index indicates a magnitude of a use load of each processor in a queue, and is a value that decreases as the number of processors allocated to the queue increases and increases as a data storage frequency to the queue from each processor increases. 7. The storage system according to claim 6, wherein the controller is configured to estimate a use load index of the first queue and a use load index of the second queue for a hypothetical case where allocation switching is executed in which a processor, in the plurality of processors allocated to the first queue, with a lowest frequency of data storage frequency to the first queue is allocated to a second queue, in the plurality of queues, with a smallest use load index, andthe controller is configured to execute the allocation switching in which the processor with the lowest frequency is allocated to the second queue, when the use load index of the first queue estimated is larger than the use load index of the second queue estimated. 8. The storage system according to claim 7, wherein the use load index is a value based on a product of reciprocal of the number of processors allocated to a queue and a sum of data storage frequencies from the processors to the queue. 9. A storage control method for data in a storage system, the storage system including: a controller including a plurality of processors; an interface device to which a storage device is coupled; and a plurality of queues associated with the interface device, the queues including a private queue and a public queue,wherein the private queue is allocated with only single processor from the plurality of processors,wherein the public queue is a queue allocate with multiple ones of the plurality of processors other than the single processor, andthe method comprising:causing the controller,when data transmitted from a processor to the interface device is data issued from the single processor, to store the data in the private queue without executing exclusion processing, andwhen data transmitted from a processor to the interface device is data issued from the multiple ones of the plurality of processors, to store the data in the public queue after executing the exclusion processing;and in a case where allocation switching between the single processor allocated to the private queue and one of the multiple ones of the plurality of processors allocated to the public queue is executed and a public frequency for which data is stored in the public queue is smaller than before the allocation switching by a predetermined threshold value or more, execute the allocation switching.
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이 특허에 인용된 특허 (11)
Abramson Kenneth D. (Seattle WA) Butts ; Jr. H. Bruce (Redmond WA) Orbits David A. (Redmond WA), Affinity scheduling of processes on symmetric multiprocessing systems.
Brenner, Larry Bert; Browning, Luke Matthew; Srinivas, Mysore Sathyanarayana; VanFleet, James William, Apparatus and method for initial load balancing in a multiple run queue system.
McBride Gregory E. (Tucson AZ) Pence Jerry W. (Tucson AZ) Van Hise David G. (Tucson AZ), Channel path load balancing, through selection of storage volumes to be processed, for long running applications.
Boland Vernon K. ; Brasche Kevin R. ; Smith Kenneth A., Method for load balancing a per processor affinity scheduler wherein processes are strictly affinitized to processors an.
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