Virtual FPGA management and optimization system
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H03K-019/177
G06F-017/50
G06F-015/78
출원번호
US-0812411
(2017-11-14)
등록번호
US-10164639
(2018-12-25)
발명자
/ 주소
Roberts, David A.
Kegel, Andrew G.
Mednick, Elliot H.
출원인 / 주소
Advanced Micro Devices, Inc.
대리인 / 주소
Liang & Cheng, PC
인용정보
피인용 횟수 :
0인용 특허 :
9
초록▼
A macro scheduler includes a resource tracking module configured to update a database enumerating a plurality of macro components of a set of field programmable gate array (FPGA) devices, a communication interface configured to receive from a first client device a first design definition indicating
A macro scheduler includes a resource tracking module configured to update a database enumerating a plurality of macro components of a set of field programmable gate array (FPGA) devices, a communication interface configured to receive from a first client device a first design definition indicating one or more specified macro components for a design, resource allocation logic configured to allocate a first set of macro components for the design by allocating one of the plurality of macro components for each of the one or more specified macro components indicated in the first design definition, and configuration logic configured to implement the design in the set of FPGA devices by configuring the first set of allocated macro components according to the first design definition.
대표청구항▼
1. A macro scheduler, comprising: a resource tracking module configured to update a database enumerating a plurality of macro components of a set of field programmable gate array (FPGA) devices;a communication interface configured to receive from a first client device a first design definition indic
1. A macro scheduler, comprising: a resource tracking module configured to update a database enumerating a plurality of macro components of a set of field programmable gate array (FPGA) devices;a communication interface configured to receive from a first client device a first design definition indicating one or more specified macro components for a design;resource allocation logic configured to allocate a first set of macro components for the design by allocating one of the plurality of macro components for each of the one or more specified macro components indicated in the first design definition; andconfiguration logic configured to implement the design in the set of FPGA devices by configuring the first set of allocated macro components according to the first design definition. 2. The macro scheduler of claim 1, wherein the first design definition comprises a macro graph defining connections between the one or more specified macro components and indicating a type of each of the one or more specified macro components. 3. The macro scheduler of claim 2, wherein: the one or more specified macro components comprise one or more specified tiles, one or more specified fixed function units, and one or more specified registers;the first design definition further indicates a bitfile for each of the one or more specified tiles; andfor each specified tile of the one or more specified tiles, the configuration logic is configured to program an allocated tile in the first set of macro components based on the bitfile for the specified tile. 4. The macro scheduler of claim 1, wherein the resource tracking module is further configured to associate each of the first set of macro components with a network address of the first client device and with a first task requested by the first client device. 5. The macro scheduler of claim 1, wherein the resource tracking module is further configured to, for each macro component of the plurality of macro components, record in the database a location of the macro component in the set of FPGA devices and an availability of the macro component. 6. The macro scheduler of claim 1, further comprising synthesis logic configured to: during execution of a task in an initial configuration of the set of FPGA devices, wherein the initial configuration is indicated by the first design definition, generate an optimized configuration for the design, wherein the configuration logic is further configured to reprogram the set of FPGA devices to replace the initial configuration with the optimized configuration prior to restarting execution of the task in the optimized configuration of the set of FPGA devices; andgenerate a remap notification correlating initial port locations in the initial configuration with optimized port locations in the optimized configuration. 7. The macro scheduler of claim 1, wherein the first design definition comprises a definition for an accelerator, and wherein the resource allocation logic is further configured to: schedule execution in the accelerator of a first task from the first client device during a first time period, andschedule execution in the accelerator of a second task from a second client device during a second time period. 8. The macro scheduler of claim 1, wherein the resource allocation logic is further configured to allocate a second set of the plurality of macro components for a second design defined by a second design definition received from a second client device, wherein a first subset of macro components in the first set of macro components is located in the same FPGA device of the set of FPGA devices as a second subset of macro components in the second set of macro components. 9. The macro scheduler of claim 1, wherein the first set of macro components comprises macro components of at least two different FPGA devices of the plurality of FPGA devices. 10. A method, comprising: updating a database enumerating a plurality of macro components of a set of field programmable gate array (FPGA) devices;receiving from a first client device a first design definition indicating one or more specified macro components for a design;allocating a first set of macro components for the design by allocating one of the plurality of macro components for each of the one or more specified macro components indicated in the first design definition; andimplementing the design in the set of FPGA devices by configuring the first set of allocated macro components according to the first design definition. 11. The method of claim 10, wherein: the one or more specified macro components comprise one or more specified tiles;the first design definition further indicates a bitfile for each of the one or more specified tiles; andthe method further comprises: for each specified tile of the one or more specified tiles, programming an allocated tile in the first set of macro components based on the bitfile for the specified tile. 12. The method of claim 10, further comprising: associating each of the first set of macro components with a network address of the first client device and with a first task requested by the first client device. 13. The method of claim 10, further comprising: for each macro component of the plurality of macro components, recording in the database a location of the macro component in the set of FPGA devices and an availability of the macro component. 14. The method of claim 10, further comprising: during execution of a task in an initial configuration of the set of FPGA devices, wherein the initial configuration is indicated by the first design definition, generating an optimized configuration for the design;reprogramming the set of FPGA devices to replace the initial configuration with the optimized configuration prior to restarting execution of the task in the optimized configuration of the set of FPGA devices; andgenerating a remap notification correlating initial port locations in the initial configuration with optimized port locations in the optimized configuration. 15. The method of claim 10, wherein the first design definition comprises a definition for an accelerator, and wherein the method further comprises: scheduling execution in the accelerator of a first task from the first client device during a first time period, andscheduling execution in the accelerator of a second task from a second client device during a second time period. 16. The method of claim 10, further comprising: allocating a second set of the plurality of macro components for a second design defined by a second design definition received from a second client device, wherein a first subset of macro components in the first set of macro components is located in the same FPGA device of the set of FPGA devices as a second subset of macro components in the second set of macro components. 17. A system, comprising: a set of field programmable gate array (FPGA) devices comprising a plurality of macro components;a database configured to enumerate the plurality of macro components; anda standalone macro scheduler, comprising: a resource tracking module configured to update the database;a communication interface configured to receive from a first client device a first design definition indicating one or more specified macro components for a design;resource allocation logic configured to allocate a first set of macro components for the design by allocating one of the plurality of macro components for each of the one or more specified macro components indicated in the first design definition; andconfiguration logic configured to implement the design in the set of FPGA devices by configuring the first set of allocated macro components according to the first design definition. 18. The system of claim 17, further comprising a first client device, wherein the standalone macro scheduler further comprises: an application programming interface (API) configured to initiate the allocating by the resource allocation logic and the configuring by the configuration logic in response to commands from the first client device. 19. The system of claim 17, wherein each of one or more FPGA devices of the set of FPGA devices comprises a local macro scheduler configured to determine a placement for at least one of the allocated macro components in the one or more FPGA devices. 20. The system of claim 17, further comprising a plurality of network channels connecting the set of FPGA devices to the standalone macro scheduler.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (9)
Ramanathan,Shriram; Kim,Sarah E.; Morrow,Patrick R., 3D integrated circuits using thick metal for backside connections and offset bumps.
Bansal, Nikhil; Hildrum, Kirsten Weale; Rajan, Deepak; Wolf, Joel Leonard, Methods and systems for assigning non-continual jobs to candidate processing nodes in a stream-oriented computer system.
Freitag ; Jr. William W., Network interface unit including a microcontroller having multiple configurable logic blocks, with a test/program bus for performing a plurality of selected functions.
New Bernard J. ; Johnson Robert Anders ; Wittig Ralph ; Mohan Sundararajarao, Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.