A protection device is provided that is placed in series connection between an input or signal node and a node to be protected. If the node to be protected is a relatively high impedance node, such as the gate of a MOSFET, then the protection device need not carry much current. This enables it to be
A protection device is provided that is placed in series connection between an input or signal node and a node to be protected. If the node to be protected is a relatively high impedance node, such as the gate of a MOSFET, then the protection device need not carry much current. This enables it to be built to be very fast. This enables it to respond rapidly to an overvoltage event so as to protect the circuit connected to the node to be protected. The protection device may be used in conjunction with other protection cells that offer greater current carrying capability and controllable trigger voltages, but which are intrinsically slower acting.
대표청구항▼
1. An overvoltage protection device comprising: a first device node;a node to be protected;a first field effect transistor having a first current flow node, a second current flow node, and a gate, wherein the first current flow node is operatively coupled to the first device node, wherein the second
1. An overvoltage protection device comprising: a first device node;a node to be protected;a first field effect transistor having a first current flow node, a second current flow node, and a gate, wherein the first current flow node is operatively coupled to the first device node, wherein the second current flow node is operatively coupled to the node to be protected, wherein the gate is configured to receive a fixed voltage, wherein the first field effect transistor is conductive when a voltage difference between the gate and either of the first and second current flow nodes is less than a threshold voltage, wherein the first field effect transistor acts to limit or prevent current flow when the voltage difference exceeds the threshold voltage, and wherein the first field effect transistor includes one or more field plates extending from a via coupled to a top gate region; andan overvoltage protection cell connected between the first current flow node and a current discharge path, wherein the overvoltage protection cell is normally high impedance. 2. An overvoltage protection device as claimed in claim 1 in which the first field effect transistor is a depletion mode device. 3. An overvoltage protection device as claimed in claim 1 in which the first field effect transistor is a junction field effect transistor. 4. An overvoltage protection device as claimed in claim 1, in which the first current flow node is a drain of the first field effect transistor, and the second current flow node is a source of the first field effect transistor. 5. An overvoltage protection device as claimed in claim 4, in which the source of the first field effect transistor is operatively connected to the node to be protected, and the drain of the first field effect transistor is operatively connected to the first device node. 6. An overvoltage protection device as claimed in claim 1 wherein the gate of the first field effect transistor is connected to ground or to Vss. 7. An overvoltage protection device as claimed in claim 6 wherein the first field effect transistor is an N type device. 8. An overvoltage protection device as claimed in claim 1 wherein the gate of the first field effect transistor is connected to a positive supply or Vdd and the transistor is a P type device. 9. An overvoltage protection device as claimed in claim 1 further comprising a second field effect transistor operatively coupled between the first current flow node of the first field effect transistor and the first device node, and wherein the gate of the second field effect transistor is coupled to the first current flow node of the first field effect transistor. 10. An overvoltage protection device as claimed in claim 1 further comprising a plurality of field effect transistors coupled in series between the node to be protected and the first device node, and a potential divider configured to provide respective potentials to gates of at least one of the plurality of field effect transistors, wherein the plurality of field effect transistors comprises the first field effect transistor. 11. An overvoltage protection device as claimed in claim 1 further comprising a plurality of field effect transistors connected in series between the node to be protected and the input, wherein the plurality of field effect transistors comprises at least one N type field effect transistor and at least one P type field effect transistor, and wherein the plurality of field effect transistors comprises the first field effect transistor. 12. An overvoltage protection device as claimed in claim 1, wherein the overvoltage protection cell is connected between the first current flow node and the current discharge path, and wherein the overvoltage protection cell is also connected between the first device node and the current discharge path. 13. An overvoltage protection device as claimed in claim 1, wherein the first field effect transistor is configured to pinch off at a first voltage, and wherein the overvoltage protection cell is configured to trigger at a second voltage that is greater than the first voltage. 14. A circuit or integrated circuit including an overvoltage protection device as claimed in claim 1. 15. A method of protecting a node to be protected from an electrostatic discharge (ESD) overvoltage event, the method comprising: placing a voltage controlled resistance in a signal path to the node to be protected, wherein the voltage controlled resistance comprises a transistor including one or more field plates coupled to a via that extends from a top gate region of the transistor to cover a portion of a channel region of the transistor;coupling a gate of the voltage controlled resistance to a fixed voltage;increasing the resistance of the voltage controlled resistance in response to the voltage in the signal path exceeding a first threshold voltage;placing a voltage controlled conduction path between an input node and a supply rail so as to open up a discharge path for current from the input node to the supply rail when the voltage thereon exceeds a second threshold voltage greater than the first threshold voltage; andwherein the voltage controlled resistance is operatively coupled between the input node and the node to be protected. 16. A method as claimed in claim 15 in which the voltage controlled resistance is a JFET, and the JFET is responsive to the ESD overvoltage event to limit current flow in less than 10 nanoseconds. 17. A method as claimed in claim 15 in which the voltage controlled resistance is a JFET, and the JFET is responsive to the ESD overvoltage event to limit current flow in less than 3 nanoseconds. 18. An electronic system comprising: one or more protection junction field effect transistors (JFETs) connected between an input node and a node to be protected, wherein the one or more protection JFETs provide overvoltage blocking between the input node and the node to be protected in response to an electrostatic discharge (ESD) event at the input node, and wherein at least a first JFET of the one or more JFETs comprises: a gate configured to receive a fixed voltage;one or more field plates covering a portion of a channel region between a drain region and the gate, the one or more field plates configured to modify an electric field gradient at a surface of the channel region by different amounts at different places; anda protection bipolar device connected between the input node and a discharge node, wherein the protection bipolar device transitions from a high impedance state to a low impedance state in response to the ESD event at the input node. 19. The electronic system of claim 18, wherein the channel region and the drain region have a first doping type, wherein the one or more protection JFETs further comprises: a top gate region of a second doping type in the channel region; anda via connected to the top gate region, the one or more field plates extending from the via. 20. The electronic system of claim 18, wherein the one or more field plates include at least a first field plate of a first length and a second field plate of a second length that is different from the first length.
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