Systems and methods for rapid processing and storage of data
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-012/00
G06F-013/00
G06F-012/02
G06F-012/0866
H04L-012/947
출원번호
US-0389049
(2016-12-22)
등록번호
US-10185655
(2019-01-22)
발명자
/ 주소
Stalzer, Mark A.
출원인 / 주소
California Institute of Technology
대리인 / 주소
KPPB LLP
인용정보
피인용 횟수 :
0인용 특허 :
11
초록▼
Systems and methods of building massively parallel computing systems using low power computing complexes in accordance with embodiments of the invention are disclosed. A massively parallel computing system in accordance with one embodiment of the invention includes at least one Solid State Blade con
Systems and methods of building massively parallel computing systems using low power computing complexes in accordance with embodiments of the invention are disclosed. A massively parallel computing system in accordance with one embodiment of the invention includes at least one Solid State Blade configured to communicate via a high performance network fabric. In addition, each Solid State Blade includes a processor configured to communicate with a plurality of low power computing complexes interconnected by a router, and each low power computing complex includes at least one general processing core, an accelerator, an I/O interface, and cache memory and is configured to communicate with non-volatile solid state memory.
대표청구항▼
1. A blade server, comprising: a plurality of computing complexes;an on-server router;a processor configured to communicate with the plurality of computing complexes, wherein the processor is interconnected to the plurality of computing complexes by the on-server router;wherein each computing comple
1. A blade server, comprising: a plurality of computing complexes;an on-server router;a processor configured to communicate with the plurality of computing complexes, wherein the processor is interconnected to the plurality of computing complexes by the on-server router;wherein each computing complex comprises:a System on Chip that includes at least one general processing core, an associated cache memory, an I/O interface, and a memory controller, and wherein the system on chip is packaged in a stacked 3D structure with a memory; anda non-volatile memory component configured in a RAID configuration that is separate from and connected to the system on chip;wherein a general processing core in a given computing complex is configured to use the memory controller to directly read and write data to the non-volatile memory component within the given computing complex;wherein general processing cores in the plurality of computing complexes are configured to directly read from and write data to the non-volatile memory component to which they are connected in parallel;wherein the on-server router is configured to (1) connect the plurality of computing complexes using individual interconnects and (2) provide at least one interconnect to at least one port of a network fabric; andwherein the blade server is configured to communicate with a plurality of blade servers via the network fabric;wherein the processor is configured to generate an index and distribute a fraction of the index to each of the plurality of computing complexes for storage within the memory of each computing complex;wherein the processor is configured to broadcast, via the router, lookup requests with respect to data stored within the plurality of computing complexes to the general processing cores within the plurality of computing complexes via the interconnects with the router; andwherein the general processing cores are configured to search for data requested by the lookup requests in parallel using the fraction of the distributed index stored in the package on package memory of each of the plurality of computing complexes. 2. A parallel computing system, comprising: at least one Solid State Blade configured to communicate via a network fabric;wherein each Solid State Blade comprises a plurality of computing complexes, an on-server router, and a processor configured to communicate with the plurality of computing complexes, wherein the processor is interconnected to the plurality of computing complexes by the on-server router;wherein each computing complex comprises: a System on Chip that includes at least one general processing core, an associated cache memory, an I/O interface, and a memory controller; and wherein the system on chip is packaged in a stacked 3D structure with a memory;wherein each computing complex is configured to communicate with an associated non-volatile memory component that is separate from and connected to the system on chip;wherein a general processing core in a given computing complex is configured to use the memory controller to directly read and write data to the non-volatile memory component within the given computing complex and the general processing cores in the plurality of computing complexes are configured to directly read and write data to the non-volatile memory component to which they are connected in parallel;wherein the on-server router is configured to (1) connect the plurality of computing complexes using individual interconnects and (2) provide at least one interconnect to at least one port of a network fabric;wherein the at least one Solid State Blade is configured to communicate with a plurality of Solid State Blades via the network fabric;wherein the processor is configured to generate an index and distribute a fraction of the index to each of the plurality of computing complexes for storage within the package on package memory of each computing complex;wherein the processor is configured to broadcast, via the router, lookup requests with respect to data stored within the plurality of computing complexes to the general processing cores within the plurality of computing complexes via the interconnects with the router; andwherein the general processing cores are configured to search for data requested by the lookup requests in parallel using the fraction of the distributed index stored in the memory of each of the plurality of computing complexes. 3. The parallel computing complex of claim 2, wherein the non-volatile memory component is NAND Flash memory. 4. The parallel computing complex of claim 2, wherein the computing complex is configured to communicate with the non-volatile memory at a rate of at least 200 MB/s. 5. The parallel computing complex of claim 2, wherein each computing complex is a System on Chip with Package on Package DRAM memory. 6. The parallel computing system of claim 2, wherein at least one non-volatile memory component is configured in a RAID configuration. 7. The parallel computing system of claim 2, wherein the plurality of computing complexes are directly connected. 8. The parallel computing system of claim 2, further comprising a plurality of Solid State Blades interconnected via the network fabric. 9. The parallel computing system of claim 2, wherein each of the at least one non-volatile memory components dedicated to a computing complex is packaged by Package on Package to the computing complex. 10. The parallel computing system of claim 2, wherein a first computing complex is configured to access data within a non-volatile memory component that is dedicated to a second computing complex by requesting the data from the second computing complex via the router. 11. The parallel computing complex of claim 2, where a software RAID configuration is implemented across all of the non-volatile memory components of each of the plurality of computing complexes. 12. The parallel computing complex of claim 2, wherein each interconnect is configured to provide data rates of at least 500 MB/s. 13. The parallel computing complex of claim 2, wherein the interconnect between the router and the processor is configured to provide data rates of at least 25 GB/s. 14. The parallel computing complex of claim 2, comprising at least 32 computing complexes. 15. The parallel computing complex of claim 2, wherein the I/O interface is configured to communicate at a rate of at least 500 MB/s. 16. The parallel computing complex of claim 2, wherein each computing complex directly reads and writes data to a non-volatile memory component configured as a RAID array. 17. The parallel computing complex of claim 16, wherein the RAID array is implemented using the memory controller incorporated in each computing complex, and wherein the memory controller is a RAID controller. 18. The parallel computing complex of claim 2, wherein the I/O between the computing complex and other devices is managed by the I/O interface. 19. The parallel computing complex of claim 2, wherein the router is a programmable router. 20. The parallel computing complex of claim 2, wherein the at least one Solid State Blade is programmable using an Open Computing Language (Open CL) and triplestores.
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