최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0119794 (2018-08-31) |
등록번호 | US-10186523 (2019-01-22) |
발명자 / 주소 |
|
출원인 / 주소 |
|
대리인 / 주소 |
|
인용정보 | 피인용 횟수 : 0 인용 특허 : 587 |
An integrated circuit includes a first gate electrode track and a second gate electrode track. The first gate electrode track includes a first gate electrode feature that forms an n-channel transistor as it crosses an n-diffusion region. The first gate electrode track does not cross a p-diffusion re
An integrated circuit includes a first gate electrode track and a second gate electrode track. The first gate electrode track includes a first gate electrode feature that forms an n-channel transistor as it crosses an n-diffusion region. The first gate electrode track does not cross a p-diffusion region. The second gate electrode track includes a second gate electrode feature that forms a p-channel transistor as it crosses a p-diffusion region. The second gate electrode track does not cross an n-diffusion region. The integrated circuit also includes a linear shaped conductor that crosses both the first and second gate electrode features in a reference direction perpendicular to the first and second gate electrode tracks. The linear shaped conductor provides electrical connection between the first and second gate electrode features.
1. A semiconductor chip, comprising: gate electrode features formed within a region of the semiconductor chip, the gate electrode features formed in part based on corresponding gate electrode feature layout shapes used as an input to a lithography process, the gate electrode feature layout shapes po
1. A semiconductor chip, comprising: gate electrode features formed within a region of the semiconductor chip, the gate electrode features formed in part based on corresponding gate electrode feature layout shapes used as an input to a lithography process, the gate electrode feature layout shapes positioned in accordance with a gate horizontal grid that includes at least seven gate gridlines, wherein all gate gridlines extend in a y-direction, wherein adjacent gate gridlines are separated from each other by a gate pitch, each gate electrode feature layout shape in the region having a substantially rectangular shape and positioned to extend lengthwise in the y-direction in a substantially centered manner along an associated gate gridline, wherein each gate gridline has at least one gate electrode feature layout shape positioned thereon, wherein at least one gate electrode feature layout shape within the region corresponds to a gate electrode feature that forms at least one gate electrode of at least one transistor of a first transistor type and does not form a gate electrode of a transistor of a second transistor type, wherein at least one gate electrode feature layout shape within the region corresponds to a gate electrode feature that forms at least one gate electrode of at least one transistor of the second transistor type and does not form a gate electrode of a transistor of the first transistor type;at least six gate contact structures formed within the region of the semiconductor chip, the at least six gate contact structures formed in part utilizing corresponding at least six gate contact structure layout shapes as an input to a lithography process, wherein at least six gate electrode features within the region have a respective top surface in physical and electrical contact with a corresponding one of the at least six gate contact structures, each of the at least six gate contact structure layout shapes having a substantially rectangular shape with a corresponding length greater than a corresponding width and with the corresponding length oriented in an x-direction, each of the at least six gate contact structure layout shapes positioned and sized to overlap both edges of the gate electrode feature layout shape corresponding to the gate electrode feature to which it is in physical and electrical contact; anda first-metal layer formed above top surfaces of the gate electrode features within the region of the semiconductor chip, the first-metal layer positioned first in a stack of metal layers counting upward from top surfaces of the gate electrode features, the first-metal layer separated from the top surfaces of the gate electrode features by at least one insulator material, wherein the first-metal layer includes first-metal structures formed in part based on corresponding first-metal structure layout shapes used as an input to a lithography process, wherein the first-metal structure layout shapes are positioned in accordance with a first-metal vertical grid, the first-metal vertical grid including at least eight first-metal gridlines, wherein all first-metal gridlines extend in the x-direction, wherein at least eight of the at least eight first-metal gridlines have at least one first-metal structure layout shape positioned thereon, each first-metal structure layout shape in the region having a substantially rectangular shape and positioned to extend lengthwise in the x-direction in a substantially centered manner on an associated first-metal gridline,wherein the region includes at least four transistors of the first transistor type and at least four transistors of the second transistor type that collectively form part of a logic circuit, wherein electrical connections within the logic circuit collectively include at least five first-metal structures corresponding to at least five first-metal structure layout shapes respectively positioned on at least five different first-metal gridlines,wherein each transistor within the region of the semiconductor chip is formed in part by a corresponding diffusion region, wherein some diffusion regions within the region of the semiconductor chip are physically and electrically contacted by at least one diffusion contact structure, the at least one diffusion contact structure formed in part utilizing corresponding at least one diffusion contact structure layout shape as an input to a lithography process, each diffusion contact structure layout shape within the region positioned in a substantially centered manner along an associated diffusion contact gridline of a diffusion contact grid, the diffusion contact grid having a diffusion contact gridline-to-diffusion contact gridline spacing measured in the x-direction equal to the gate pitch. 2. The semiconductor chip as recited in claim 1, further comprising: a second-metal layer formed above the first-metal layer within the region of the semiconductor chip, the second-metal layer positioned second in the stack of metal layers counting upward from top surfaces of the gate electrode features, the second-metal layer separated from the first-metal layer by at least one insulator material, the second-metal layer including second-metal structures formed in part based on corresponding second-metal structure layout shapes used as an input to a lithography process, the second-metal layer layout shapes positioned in accordance with a second-metal horizontal grid, the second-metal horizontal grid including at least eight second-metal gridlines, wherein all second-metal gridlines extend in the y-direction, wherein at least eight of the at least eight second-metal gridlines have at least one second-metal structure layout shape positioned thereon, each second-metal structure layout shape in the region having a substantially rectangular shape and positioned to extend lengthwise in the y-direction in a substantially centered manner along an associated second-metal gridline,wherein some second-metal structures within the region are electrically connected to at least one first-metal structure within the region through at least one first-metal-to-second-metal via structure, each first-metal-to-second-metal via structure within the region formed in part based on corresponding first-metal-to-second-metal via structure layout shape used as an input to a lithography process, each first-metal-to-second-metal via structure layout shape within the region positioned in a substantially centered manner along an associated second-metal gridline. 3. The semiconductor chip as recited in claim 2, wherein each first-metal structure layout shape in the region has a width measured in the y-direction that is either a first width or a second width, the second width different than the first width, the first-metal layer including at least one first-metal structure formed in part by a first-metal structure layout shape that has the first width, the first-metal layer including at least one first-metal structure formed in part by a first-metal layout shape that has the second width. 4. The semiconductor chip as recited in claim 3, wherein at least one gate electrode feature within the region that forms at least one gate electrode of at least one transistor of the first transistor type and does not form a gate electrode of a transistor of the second transistor type is electrically connected to at least one gate electrode feature within the region that forms at least one gate electrode of at least one transistor of the second transistor type and does not form a gate electrode of a transistor of the first transistor type through an electrical connection that includes at least one first-metal structure and at least one second-metal structure. 5. The semiconductor chip as recited in claim 2, wherein the at least six gate contact structure layout shapes are positioned in accordance with a contact vertical grid, the contact vertical grid including contact gridlines extending in the x-direction, each of the at least six gate contact structure layout shapes positioned to extend lengthwise in the x-direction in a substantially centered manner along an associated contact gridline, and at least two of the at least six gate contact structure layout shapes positioned to also extend lengthwise in the x-direction in a substantially centered manner along a corresponding first-metal gridline. 6. The semiconductor chip as recited in claim 2, wherein each first-metal structure layout shape in the region has a width measured in the y-direction that is one of a plurality of widths, the plurality of widths including a first width and a second width, the first width smaller than the second width, the first-metal layer including at least one first-metal structure formed in part by a first-metal structure layout shape that has the first width, the first-metal layer including at least one first-metal structure formed in part by a first-metal structure layout shape that has the second width, wherein each first-metal-to-second-metal via structure that contacts a first-metal structure formed in part by a first-metal structure layout shape having the first width is formed at least in part by a first-metal-to-second-metal via structure layout shape that is intersected by a corresponding first-metal gridline. 7. The semiconductor chip as recited in claim 6, wherein each first-metal-to-second-metal via structure layout shape is intersected by a corresponding first-metal gridline. 8. The semiconductor chip as recited in claim 2, wherein adjacent second-metal gridlines are separated from each other by a second-metal pitch, the second-metal pitch equal to the gate pitch, the second-metal horizontal grid aligned with the diffusion contact grid. 9. The semiconductor chip as recited in claim 8, wherein all second-metal structure layout shapes in the region of the semiconductor chip have a same width as measured in the x-direction. 10. The semiconductor chip as recited in claim 9, further comprising: a third-metal layer formed above the second-metal layer within the region of the semiconductor chip, the third-metal layer positioned third in the stack of metal layers counting upward from top surfaces of the gate electrode features, the third-metal layer separated from the second-metal layer by at least one insulator material, the third-metal layer including third-metal structures formed in part based on corresponding third-metal structure layout shapes used as an input to a lithography process, the third-metal layer layout shapes positioned in accordance with a third-metal vertical grid, the third-metal vertical grid including at least eight third-metal gridlines, wherein all third-metal gridlines extend in the x-direction, wherein at least eight of the at least eight third-metal gridlines have at least one third-metal structure layout shape positioned thereon, each third-metal structure layout shape in the region having a substantially rectangular shape and positioned to extend lengthwise in the x-direction in a substantially centered manner along an associated third-metal gridline,wherein some third-metal structures within the region are electrically connected to at least one second-metal structure within the region through at least one second-metal-to-third-metal via structure, each second-metal-to-third-metal via structure within the region formed in part based on corresponding second-metal-to-third-metal via structure layout shape used as an input to a lithography process, wherein at least one second-metal-to-third-metal via structure layout shape within the region is positioned in a substantially centered manner along an associated third-metal gridline. 11. The semiconductor chip as recited in claim 10, wherein each second-metal-to-third-metal via structure layout shape is intersected by a corresponding second-metal gridline. 12. The semiconductor chip as recited in claim 10, wherein each second-metal structure layout shape in the region is positioned next to at least one other second-metal structure layout shape on a first side at a second-metal pitch and is positioned next to at least one other second-metal structure layout shape on a second side at the second-metal pitch, wherein the second-metal pitch is measured in the x-direction and is equal to the gate pitch. 13. The semiconductor chip as recited in claim 1, wherein the at least four transistors of the first transistor type and the at least four transistors of the second transistor type within the region collectively form part of an inverting two-to-one multiplexer. 14. The semiconductor chip as recited in claim 1, wherein at least one of the at least six gate contact structures is in physical and electrical contact with, and is substantially centered in the x-direction on, a gate electrode feature within the region that forms at least one gate electrode of at least one transistor of the first transistor type and that does not form a gate electrode of a transistor of the second transistor type. 15. The semiconductor chip as recited in claim 1, wherein each of the at least six gate contact structure layout shapes is intersected by a corresponding gate gridline. 16. The semiconductor chip as recited in claim 1, wherein the first-metal layer includes at least eight first-metal structure layout shapes positioned on four first-metal layer gridlines such that a different two of the at least eight first-metal structure layout shapes is positioned on each of the four first-metal layer gridlines, wherein each of the at least eight first-metal structure layout shapes is positioned next to and spaced apart from at least one other first-metal structure layout shape at a first-metal pitch. 17. The semiconductor chip as recited in claim 1, wherein the at least eight of the at least eight first-metal gridlines that have at least one first-metal structure layout shape positioned thereon are spaced at a first-metal pitch. 18. The semiconductor chip as recited in claim 1, further comprising: a second-metal layer formed above the first-metal layer within the region of the semiconductor chip, the second-metal layer positioned second in the stack of metal layers counting upward from top surfaces of the gate electrode features, the second-metal layer separated from the first-metal layer by at least one insulator material, the second-metal layer including second-metal structures formed in part based on corresponding second-metal structure layout shapes used as an input to a lithography process, the second-metal structure layout shapes positioned in accordance with a second-metal horizontal grid, the second-metal horizontal grid including at least eight second-metal gridlines, wherein all second-metal gridlines extend in the y-direction, wherein at least eight of the at least eight second-metal gridlines have at least one second-metal structure layout shape positioned thereon, each second-metal structure layout shape in the region having a substantially rectangular shape and positioned to extend lengthwise in the y-direction in a substantially centered manner along an associated second-metal gridline; anda third-metal layer formed above the second-metal layer within the region of the semiconductor chip, the third-metal layer positioned third in the stack of metal layers counting upward from top surfaces of the gate electrode features, the third-metal layer separated from the second-metal layer by at least one insulator material, the third-metal layer including third-metal structures formed in part based on corresponding third-metal structure layout shapes used as an input to a lithography process, the third-metal structure layout shapes positioned in accordance with a third-metal vertical grid, the third-metal vertical grid including at least eight third-metal gridlines, wherein all third-metal gridlines extend in the x-direction, wherein at least eight of the at least eight third-metal gridlines have at least one third-metal structure layout shape positioned thereon, each third-metal structure layout shape in the region having a substantially rectangular shape and positioned to extend lengthwise in the x-direction in a substantially centered manner along an associated third-metal gridline. 19. The semiconductor chip as recited in claim 18, wherein each first-metal structure layout shape in the region has a width measured in the y-direction that is one of a plurality of widths, the plurality of widths including a first width and a second width, the first width smaller than the second width, the first-metal layer including at least one first-metal structure formed in part by a first-metal structure layout shape that has the first width, the first-metal layer including at least one first-metal structure formed in part by a first-metal structure layout shape that has the second width, wherein each first-metal-to-second-metal via structure that contacts a first-metal structure formed in part by a first-metal structure layout shape having the first width is formed at least in part by a first-metal-to-second-metal via structure layout shape that is intersected by a corresponding first-metal gridline. 20. The semiconductor chip as recited in claim 18, wherein some third-metal structures within the region are electrically connected to at least one second-metal structure within the region through at least one second-metal-to-third-metal via structure, each second-metal-to-third-metal via structure formed at least in part by a second-metal-to-third-metal via structure layout shape that is intersected by a corresponding second-metal gridline. 21. The semiconductor chip as recited in claim 20, wherein each third-metal structure layout shape in the region has a width measured in the y-direction that is one of a plurality of widths, the plurality of widths including a first width and a second width, the first width smaller than the second width, the third-metal layer including at least one third-metal structure formed in part by a third-metal structure layout shape that has the first width, the third-metal layer including at least one third-metal structure formed in part by a third-metal structure layout shape that has the second width, wherein each second-metal-to-third-metal via structure that contacts a third-metal structure formed in part by a third-metal structure layout shape having the first width is formed at least in part by a second-metal-to-third-metal via structure layout shape that is intersected by a corresponding third-metal gridline. 22. The semiconductor chip as recited in claim 18, wherein the at least four transistors of the first transistor type include a first transistor of the first transistor type, wherein the at least four transistors of the second transistor type include a first transistor of the second transistor type, wherein a gate electrode feature layout shape used to form a gate electrode feature that forms a gate electrode of the first transistor of the first transistor type and a gate electrode feature layout shape used to form a gate electrode feature that forms a gate electrode of the first transistor of the second transistor type are positioned to extend lengthwise along a same gate gridline, wherein no other transistor is positioned on the same gate gridline between the gate electrode feature layout shapes used to form the gate electrode features that form the gate electrodes of the first transistor of the first transistor type and the first transistor of the second transistor type, wherein each transistor within the region of the semiconductor chip is formed in part by a corresponding diffusion region, wherein a diffusion region of the first transistor of the first transistor type is electrically connected to a diffusion region of the first transistor of the second transistor type,wherein the at least six gate contact structure layout shapes include a gate contact structure layout shape substantially centered in the x-direction on the same gate gridline at a location between the diffusion regions of the first transistor of the first transistor type and the first transistor of the second transistor type,wherein an electrical connection between the diffusion region of the first transistor of the first transistor type and the diffusion region of the first transistor of the second transistor type includes at least one first-metal structure and at least one second-metal structure,wherein the at least four transistors of the first transistor type and the at least four transistors of the second transistor type within the region collectively form part of an inverting two-to-one multiplexer. 23. The semiconductor chip as recited in claim 22, wherein adjacent second-metal gridlines are separated from each other by a second-metal pitch, the second-metal pitch equal to the gate pitch, the second-metal horizontal grid aligned with the diffusion contact grid. 24. The semiconductor chip as recited in claim 23, wherein all second-metal structure layout shapes in the region of the semiconductor chip have a same width as measured in the x-direction. 25. The semiconductor chip as recited in claim 1, wherein the at least four transistors of the first transistor type are collectively separated from the at least four transistors of the second transistor type by an inner region that does not include another transistor. 26. The semiconductor chip as recited in claim 25, wherein at least one of the at least six gate contact structure layout shapes is positioned over the inner region and forms a gate contact structure that is in physical and electrical contact with, and is substantially centered in the x-direction on, a gate electrode feature within the region that forms at least one gate electrode of at least one transistor. 27. A semiconductor chip, comprising: gate electrode features formed within a region of the semiconductor chip, the gate electrode features formed in part based on corresponding gate electrode feature layout shapes used as an input to a lithography process, the gate electrode feature layout shapes positioned in accordance with a gate horizontal grid that includes at least seven gate gridlines, wherein adjacent gate gridlines are separated from each other by a gate pitch, each gate electrode feature layout shape in the region having a substantially rectangular shape and positioned to extend lengthwise in a y-direction in a substantially centered manner along an associated gate gridline, wherein each gate gridline has at least one gate electrode feature layout shape positioned thereon, wherein at least one gate electrode feature layout shape within the region corresponds to a gate electrode feature that forms at least one gate electrode of at least one transistor of a first transistor type and does not form a gate electrode of a transistor of a second transistor type, wherein at least one gate electrode feature layout shape within the region corresponds to a gate electrode feature that forms at least one gate electrode of at least one transistor of the second transistor type and does not form a gate electrode of a transistor of the first transistor type;a number of gate contact structures formed within the region of the semiconductor chip, the gate contact structures formed in part utilizing corresponding gate contact structure layout shapes as an input to a lithography process, wherein each gate electrode feature that forms any transistor gate electrode within the region has a respective top surface in physical and electrical contact with a corresponding gate contact structure formed at least in part from a gate contact structure layout shape having a substantially rectangular shape, wherein each gate contact structure that contacts a given gate electrode feature that forms any transistor gate electrode does not contact another gate electrode feature, wherein any gate contact structure layout shape that has a corresponding length greater than or equal to a corresponding width is oriented to have its corresponding length extend in an x-direction; anda first-metal layer formed above top surfaces of the gate electrode features within the region of the semiconductor chip, the first-metal layer positioned first in a stack of metal layers counting upward from top surfaces of the gate electrode features, the first-metal layer separated from the top surfaces of the gate electrode features by at least one insulator material, the first-metal layer including first-metal structures formed in part based on corresponding first-metal structure layout shapes used as an input to a lithography process,wherein each transistor within the region is formed in part by a corresponding diffusion region, each diffusion region formed in part utilizing a corresponding diffusion region layout shape as an input to a lithography process, wherein each diffusion region that forms part of any transistor within the region is formed at least in part by a corresponding diffusion region layout shape that has a substantially rectangular shape,wherein the region includes at least four transistors of the first transistor type and at least four transistors of the second transistor type that collectively form a portion of a multiplexer or a portion of a latch, wherein at least two first-metal structures form portions of one or more electrical connections within the multiplexer or the latch. 28. A semiconductor chip, comprising: gate electrode features formed within a region of the semiconductor chip, the gate electrode features formed in part based on corresponding gate electrode feature layout shapes used as an input to a lithography process, the gate electrode feature layout shapes positioned in accordance with a gate horizontal grid that includes a number of gate gridlines, wherein adjacent gate gridlines are separated from each other by a gate pitch, each gate electrode feature layout shape in the region having a substantially rectangular shape and positioned to extend lengthwise in a y-direction in a substantially centered manner along an associated gate gridline, wherein each gate gridline has at least one gate electrode feature layout shape positioned thereon, wherein at least one gate electrode feature layout shape within the region corresponds to a gate electrode feature that forms at least one gate electrode of at least one transistor of a first transistor type and does not form a gate electrode of a transistor of a second transistor type, wherein at least one gate electrode feature layout shape within the region corresponds to a gate electrode feature that forms at least one gate electrode of at least one transistor of the second transistor type and does not form a gate electrode of a transistor of the first transistor type;a number of gate contact structures formed within the region of the semiconductor chip, the gate contact structures formed in part utilizing corresponding gate contact structure layout shapes as an input to a lithography process, wherein each of at least six gate electrode features within the region has a respective top surface in physical and electrical contact with a corresponding gate contact structure formed at least in part from a gate contact structure layout shape having a substantially rectangular shape, wherein each gate contact structure is centered in an x-direction on the gate electrode feature with which it physical contacts, wherein each gate contact structure layout shape that has the substantially rectangular shape has a corresponding length greater than or equal to a corresponding width and is oriented to have its corresponding length extend in the x-direction, wherein each of the number of gate contact structures is in physical contact with only one of any of the gate electrode features; anda first-metal layer formed above top surfaces of the gate electrode features within the region of the semiconductor chip, the first-metal layer positioned first in a stack of metal layers counting upward from top surfaces of the gate electrode features, the first-metal layer separated from the top surfaces of the gate electrode features by at least one insulator material, the first-metal layer including at least two first-metal structures formed in part based on corresponding first-metal structure layout shapes used as an input to a lithography process, the at least two first-metal structures forming portions of one or more electrical connections within the region of the semiconductor chip,wherein each transistor within the region is formed in part by a corresponding diffusion region, each diffusion region formed in part utilizing a corresponding diffusion region layout shape as an input to a lithography process, wherein each diffusion region that forms part of any transistor within the region is formed at least in part by a corresponding diffusion region layout shape that has a substantially rectangular shape.
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