Interconnect structure and fabricating method thereof
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-023/52
H01L-023/532
H01L-023/528
H01L-021/768
H01L-021/3213
H01L-023/522
출원번호
US-0415699
(2017-01-25)
등록번호
US-10204859
(2019-02-12)
발명자
/ 주소
Lee, Hong-Ji
Huang, Min-Hsuan
출원인 / 주소
MACRONIX International Co., Ltd.
대리인 / 주소
J.C. Patents
인용정보
피인용 횟수 :
0인용 특허 :
5
초록
An interconnect structure including a substrate and a conductive pattern is provided. The conductive pattern includes a bottom portion. The bottom portion of the conductive pattern is disposed on the substrate. The conductive pattern has a notch on each of two sidewalls of the bottom portion.
대표청구항▼
1. An interconnect structure, comprising: a substrate;a conductive pattern comprising a bottom portion, wherein the bottom portion of the conductive pattern is disposed on the substrate, and the conductive pattern has a notch on each of two sidewalls of the bottom portion; anda dielectric layer surr
1. An interconnect structure, comprising: a substrate;a conductive pattern comprising a bottom portion, wherein the bottom portion of the conductive pattern is disposed on the substrate, and the conductive pattern has a notch on each of two sidewalls of the bottom portion; anda dielectric layer surrounding the conductive pattern, wherein a hollow is present in the notch and between the conductive pattern and the dielectric layer. 2. The interconnect structure according to claim 1, wherein a position of a minimum width of the conductive pattern is at the notch. 3. The interconnect structure according to claim 2, wherein the conductive pattern further comprises an intermediate portion and a top portion, wherein the intermediate portion is located between the top portion and the bottom portion, and a position of a maximum width of the conductive pattern is at the intermediate portion. 4. The interconnect structure according to claim 3, wherein the position of the maximum width of the conductive pattern is a transition position of a positive slope and a negative slope. 5. The interconnect structure according to claim 2, further comprising a first barrier layer disposed between the conductive pattern and the substrate. 6. The interconnect structure according to claim 5, wherein a width of the first barrier layer is greater than the minimum width of the conductive pattern. 7. The interconnect structure according to claim 5, wherein the notch is located at an interface between the conductive pattern and the first barrier layer. 8. The interconnect structure according to claim 1, further comprising a second barrier layer disposed on the conductive pattern. 9. The interconnect structure according to claim 1, further comprising a dielectric layer disposed on the substrate at two sides of the conductive pattern, wherein the notch is located between the dielectric layer and the conductive pattern. 10. The interconnect structure according to claim 1, wherein a material of the conductive pattern comprises AlCu, Al, or W. 11. A fabricating method of an interconnect structure, the fabricating method comprising: providing a substrate;forming a conductive pattern on the substrate, wherein the conductive pattern comprises a bottom portion, and the conductive pattern has a notch on each of two sidewalls of the bottom portion; andforming a dielectric layer surrounding the conductive pattern, wherein a hollow is present in the notch and between the conductive pattern and the dielectric layer. 12. The fabricating method according to claim 11, wherein a forming method of the conductive pattern comprises: forming a conductive pattern material layer on the substrate;forming a patterned mask layer on the conductive pattern material layer;performing a first etching process on the conductive pattern material layer with the patterned mask layer as a mask, wherein a first etching gas used in the first etching process comprises a Cl2 and a BCl3, and in the first etching process, a flow rate of the BCl3 is less than or equal to a flow rate of the Cl2; andperforming a second etching process on the conductive pattern material layer with the patterned mask layer as a mask after performing the first etching process, wherein a second etching gas used in the second etching process comprises the Cl2 and the BCl3, and in the second etching process, the flow rate of the BCl3 is greater than the flow rate of the Cl2. 13. The fabricating method according to claim 12, wherein a flow rate ratio of the BCl3 to the Cl2 in the first etching process is 0.3 to 1. 14. The fabricating method according to claim 12, wherein a flow rate ratio of the BCl3 to the Cl2 in the second etching process is 1.3 to 5. 15. The fabricating method according to claim 12, wherein during the second etching process, a process pressure is 2 mTorr to 30 mTorr, a source RF power is 100 W to 1500 W, and a bias RF power is 15 W to 200 W. 16. The fabricating method according to claim 12, wherein the first etching gas and the second etching gas further comprise a protective gas, respectively. 17. The fabricating method according to claim 16, wherein the protective gas comprises CH4, N2, CF4, CHF3, or a combination of the foregoing. 18. The fabricating method according to claim 11, further comprising forming a first barrier layer between the conductive pattern and the substrate. 19. The fabricating method according to claim 11, further comprising forming a second barrier layer on the conductive pattern. 20. The fabricating method according to claim 11, further comprising forming a dielectric layer on the substrate at two sides of the conductive pattern, wherein the notch is located between the dielectric layer and the conductive pattern.
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