Two-transistor devices for protecting circuits from sustained overcurrent
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H02H-003/087
H02H-003/093
H02H-001/04
출원번호
US-0216758
(2016-07-22)
등록번호
US-10205313
(2019-02-12)
발명자
/ 주소
Creech, Mark D.
출원인 / 주소
Symptote Technologies, LLC
대리인 / 주소
Thrive IP®
인용정보
피인용 횟수 :
0인용 특허 :
36
초록▼
Two-transistor devices protect electrical circuits from sustained overcurrent conditions. Some cases provide normally-on depletion mode transistors biased into enhancement mode for lower impedance during normal current conditions, and then the transistors are biased into blocking depletion mode duri
Two-transistor devices protect electrical circuits from sustained overcurrent conditions. Some cases provide normally-on depletion mode transistors biased into enhancement mode for lower impedance during normal current conditions, and then the transistors are biased into blocking depletion mode during sustained overcurrent conditions to block the current to the circuit. Optionally, the devices have only two terminals and require no auxiliary power to operate. Other cases provide protective circuitry for the transistors' gates, timing circuitry designed to ignore brief nuisance spikes, and/or timing circuitry to delay resetting the device until the current has returned to an acceptable level.
대표청구항▼
1. A device for protecting a circuit having a primary current path from a sustained overcurrent condition, comprising: a first terminal and a second terminal;a first transistor comprising a first gate, a first drain, and a first source, wherein the first transistor is an n-channel, depletion mode, n
1. A device for protecting a circuit having a primary current path from a sustained overcurrent condition, comprising: a first terminal and a second terminal;a first transistor comprising a first gate, a first drain, and a first source, wherein the first transistor is an n-channel, depletion mode, normally-on transistor;a second transistor comprising a second gate, a second drain, and a second source, wherein the second transistor is a p-channel, depletion mode, normally-on transistor; andgate drive circuitry configured to bias the first gate and the second gate;wherein the first transistor and the second transistor are arranged in series in the primary current path between the first terminal and the second terminal;wherein the first transistor and the second transistor are similarly aligned;wherein, when a first positive voltage and a normal current condition exist from the first terminal to the second terminal, the first transistor is configured to operate substantially in enhancement mode; andthe second transistor is configured to operate substantially in enhancement mode; andwherein, when a second positive voltage and a sustained overcurrent condition exist from the first terminal to the second terminal, the first transistor is configured to operate in blocking depletion mode; andthe second transistor is configured to operate in blocking depletion mode andwherein the device is configured to pass current during normal current conditions, and to substantially block current during sustained overcurrent conditions. 2. The device of claim 1, wherein the gate drive circuitry comprises two transistors in a totem pole driver stage configuration. 3. The device of claim 1, wherein the gate drive circuitry comprises a first totem pole driver stage configured to bias the first gate, and a second totem pole driver stage configured to bias the second gate. 4. The device of claim 1, further comprising a first gate protection circuitry configured to limit a voltage at the first gate to a first predetermined range; and a second gate protection circuitry configured to limit a voltage at the second gate to a second predetermined range. 5. The device of claim 1, further comprising a gate protection circuitry configured to limit a first voltage at the first gate to a first predetermined range and a second voltage at the second gate to a second predetermined range. 6. The device of claim 5, wherein the gate protection circuitry comprises a transistor with its drain in electrical communication with the first terminal, and its gate in electrical communication with the second terminal. 7. The device of claim 1, further comprising current monitoring circuitry configured to monitor the current flowing through the device. 8. The device of claim 1, further comprising voltage storage/generation circuitry configured to store charge during normal current conditions. 9. The device of claim 8, wherein the voltage storage/generation circuitry comprises at least one capacitor and at least one diode. 10. The device of claim 1, further comprising voltage storage/generation circuitry configured to store charge during sustained overcurrent conditions. 11. The device of claim 10, wherein the voltage storage/generation circuitry comprises at least one capacitor and at least one diode. 12. The device of claim 1, further comprising high/low voltage sensor circuitry configured to monitor a voltage drop between the first terminal and the second terminal. 13. The device of claim 12, wherein the high/low voltage sensor circuitry comprises at least two resistors configured to act as a voltage divider in electrical communication with the first terminal and the second terminal. 14. The device of claim 1, further comprising power good circuitry configured to monitor the electrical energy within the device. 15. The device of claim 14, wherein the power good circuitry is further configured to oscillate the device into blocking mode to store charge, and into conducting mode once sufficient charge has been stored. 16. The device of claim 14, wherein the power good circuitry comprises a plurality of transistors configured to monitor the stored electrical charge of a capacitor in electrical communication with the first terminal and the second terminal. 17. The device of claim 1, further comprising a delay blocking timer circuitry configured to delay onset of blocking depletion mode in the first transistor and the second transistor. 18. The device of claim 17, wherein the delay blocking timer circuitry comprises at least one resistor in electrical communication with at least one capacitor. 19. The device of claim 1, further comprising a delay reset timer circuitry configured to delay onset of enhancement mode following the sustained overcurrent condition.
Pryor Dennis M. (Swindon GB2) Atkins Ian P. (Swindon GB2) Challis Michael (Swindon GB2) Williams David M. (Faringdon GB2), Circuit protection arrangement.
Kumfer, Brent Charles; Greenwood, Peter James; Mooney, Brian Frederick; Papallo, Jr., Thomas Frederick; Subramanian, Kanakasabapathi, Electrical distribution system including micro electro-mechanical switch (MEMS) devices.
Premerlani, William James; Subramanian, Kanakasabapathi; O'Brien, Kathleen Ann; Park, John Norton; Kumfer, Brent Charles; Thakre, Parag, MEMS micro-switch array based on current limiting enabled circuit interrupting apparatus.
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