A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over
A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.
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1. A memory-access method for a memory system with physical memory that includes a plurality of volatile access units addressed by a corresponding plurality of volatile-storage addresses and a plurality of nonvolatile access units addressed by a corresponding plurality of nonvolatile-storage address
1. A memory-access method for a memory system with physical memory that includes a plurality of volatile access units addressed by a corresponding plurality of volatile-storage addresses and a plurality of nonvolatile access units addressed by a corresponding plurality of nonvolatile-storage addresses, the method comprising: maintaining, in the volatile access units, a table relating the volatile access units storing data to corresponding ones of the nonvolatile access units storing the same data, the volatile access units including a first volatile access unit storing first data and a first nonvolatile access unit, related to the first volatile access unit in the table, storing the first data;writing second data to the first volatile access unit without writing the second data to the first nonvolatile access unit;setting a dirty bit, in the volatile access units, identifying the first volatile access unit as dirty;maintaining a head pointer designating a head address of the nonvolatile-storage addresses, the head address corresponding to the nonvolatile access unit to receive next write data;maintaining a tail pointer designating a tail address of the nonvolatile-storage addresses, wherein the head address and the tail address define between them a sequence of the nonvolatile-storage addresses;writing the second data from the first volatile access unit to a second of the nonvolatile access units designated by the head address;advancing the head pointer to a second head address responsive to the writing of the second data; andcomparing the advanced head pointer to the tail pointer and, if a difference between the advanced head pointer and the tail pointer exceeds a threshold, reading third data from a third of the nonvolatile access units and writing the third data to the one of the nonvolatile access units designated by the advanced head pointer. 2. The method of claim 1, further comprising writing third data to the first nonvolatile access unit. 3. The method of claim 2, further comprising loading the third data from the first nonvolatile access unit to a second of the volatile access units. 4. The memory-access method of claim 1, wherein the nonvolatile-storage addresses in the sequence of the nonvolatile-storage addresses are contiguous. 5. The memory-access method of claim 4, further comprising advancing the tail pointer to exclude from the sequence of the nonvolatile-storage addresses the nonvolatile-storage address of the nonvolatile access unit from which the third data was read. 6. The memory-access method of claim 5, further comprising erasing the nonvolatile access unit from which the third data was read. 7. A non-transitory computer-readable medium having stored thereon a data structure having information defining at least a portion of an integrated-circuit memory controller, the data structure comprising: first data representing a first connection to couple to a cache memory of volatile access units with volatile access units specified by respective volatile-access-unit addresses;second data representing a second connection to couple to a nonvolatile memory with nonvolatile access units specified by respective nonvolatile-access-unit addresses; andthird data representing a memory controller coupled to the nonvolatile memory and the cache memory, the memory controller maintaining, in the volatile access units, a table identifying whether data in the volatile access units has been written to the nonvolatile access units, and maintaining, as a head nonvolatile address, the nonvolatile-access-unit address of a next nonvolatile access unit to receive write data from one of the volatile access units; andas a tail nonvolatile address, the nonvolatile-access-unit address storing an eldest of the data, the head and tail nonvolatile addresses to define between them a contiguous group of consecutive nonvolatile addresses; andfourth data representing circuitry to compare the head and tail nonvolatile addresses to initiate a garbage-collection process. 8. The medium of claim 7, the memory controller further comprising a head register to store the head nonvolatile address. 9. The medium of claim 7, the memory controller further maintaining, in the volatile access units, a second table identifying which of the nonvolatile access units contain valid data. 10. The medium of claim 7, the memory controller to maintain, in the volatile access units, a first address translation table mapping the volatile-access-unit addresses to the nonvolatile-access-unit addresses. 11. The medium of claim 10, the memory controller to maintain a second address translation table mapping the nonvolatile-access-unit addresses to the volatile-access-unit addresses.
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