Photovoltaic cell with high efficiency CIGS absorber layer with low minority carrier lifetime and method of making thereof
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-031/032
H01L-031/0392
H01L-031/0749
H01L-031/0224
출원번호
US-0034131
(2018-07-12)
등록번호
US-10211351
(2019-02-19)
발명자
/ 주소
Corson, John
Austin, Alex
Tas, Robert
Mackie, Neil
Larsson, Mats
Demirkan, Korhan
Zhang, Weijie
Titus, Jochen
Sevanna, Swati
Zubeck, Robert
Dorn, Randy
Rairkar, Asit
Rulkens, Ron
Saproo, Ajay
Vitkavage, Dan
출원인 / 주소
BEIJING APOLLO DING RONG SOLAR TECHNOLOGY CO., LTD.
대리인 / 주소
The Marbury Law Group PLLC
인용정보
피인용 횟수 :
0인용 특허 :
81
초록
A solar cell containing a plurality of CIGS absorber sublayers has a conversion efficiency of at least 13.4 percent and a minority carrier lifetime below 2 nanoseconds. The sublayers may have a different composition from each other.
대표청구항▼
1. A method of manufacturing a solar cell, comprising: providing a substrate;depositing a first electrode over the substrate;depositing at least one p-type semiconductor absorber layer over the first electrode, wherein the p-type semiconductor absorber layer comprises at least one sodium containing
1. A method of manufacturing a solar cell, comprising: providing a substrate;depositing a first electrode over the substrate;depositing at least one p-type semiconductor absorber layer over the first electrode, wherein the p-type semiconductor absorber layer comprises at least one sodium containing copper indium gallium selenide layer;depositing an n-type semiconductor layer over the p-type semiconductor absorber layer; anddepositing a second electrode over the n-type semiconductor layer;wherein the solar cell has a conversion efficiency of at least 13.4 percent and with a minority carrier lifetime below 2 nanoseconds, wherein the first electrode comprises a first transition metal layer which comprises a sodium and oxygen containing molybdenum layer,wherein the p-type semiconductor absorber layer has a band gap of 1.14 eV or higher,wherein the p-type semiconductor absorber layer has a graded composition as a function of thickness and has a majority carrier concentration of about 1×1013 to about 1×1015 cm−3,wherein the graded composition p-type semiconductor absorber layer comprises a first copper indium gallium selenide sublayer adjacent to the first electrode, and a second copper indium gallium selenide sublayer over the first sublayer, and the first sublayer has a higher ratio of Ga/(Ga+In) than the second sublayer,wherein the graded composition p-type semiconductor absorber layer further comprises a third copper indium gallium selenide sublayer over the second sublayer and adjacent to the n-type semiconductor layer, the third sublayer has a lower ratio of Cu/(Ga+In) than the first or the second sublayers, andwherein: the first sublayer has a ratio of Ga/(Ga+In) of 0.4 to 0.6, and a ratio of Cu/(Ga+In) of 0.75 to 0.9; the second sublayer has a ratio of Ga/(Ga+In) of 0.2 to 0.3, and a ratio of Cu/(Ga+In) of 0.85 to 0.99; and the third sublayer has a ratio of Ga/(Ga+In) of 0.25 to 0.35, and a ratio of Cu/(Ga+In) of 0.05 to 0.3. 2. The method of claim 1, wherein: the solar cell is located in a module; andthe module has an active area greater than or equal to 1 m2 and a conversion efficiency greater than or equal to 15.7 percent average active area. 3. The method of claim 2, wherein the module has a conversion efficiency of 15.7 to 16.1 percent average active area and the minority carrier lifetime of 1.6 nanoseconds or less. 4. The method of claim 1, wherein the solar cell has an active area of ¼ cm2 to ½ cm2 and a conversion efficiency greater than or equal to 14.4 percent average active area. 5. The method of claim 4, wherein the solar cell has the conversion efficiency of 16.6 to 18.1 percent average active area. 6. The method of claim 1, wherein the solar cell has an open circuit voltage that is greater than 550 mV. 7. The method of claim 6, wherein the solar cell has an open circuit voltage of at least 650 mV. 8. The method of claim 1, wherein the solar cell has a minority carrier lifetime of less than 1 nanosecond. 9. The method of claim 8, wherein the solar cell has a minority carrier lifetime of 0.3 to 0.8 nanoseconds. 10. The method of claim 1, wherein sodium diffuses from the first transition metal layer into the p-type semiconductor absorber layer during the step of depositing the p-type semiconductor absorber layer, and wherein the first transition metal layer comprises at least 59 atomic percent molybdenum, 5 to 40 atomic percent oxygen and 0.01 to 1.5 atomic percent sodium. 11. The method of claim 10, wherein: the first electrode further comprises a molybdenum barrier layer located over the first transition metal layer;the molybdenum barrier layer is substantially free of oxygen and has a higher density than the first transition metal layer; andsodium diffuses from the first transition metal layer through the molybdenum barrier layer into the p-type semiconductor absorber layer during the step of reactively sputtering the p-type semiconductor absorber layer. 12. The method of claim 1, wherein the p-type semiconductor absorber layer has a band gap in a range of 1.3 to 1.5 eV. 13. The method of claim 1, wherein the first electrode, the at least one p-type semiconductor absorber layer, the n-type semiconductor layer and the second electrode are deposited over the substrate which comprises a moving web substrate by sputtering with no vacuum break. 14. The method of claim 13, wherein the first sublayer is deposited at a lower temperature than the second sublayer. 15. The method of claim 14, wherein the first sublayer is deposited at a temperature of 450 to 500 C by reactive sputtering using selenium vapor and at least a first copper-indium-gallium alloy target and the second sublayer is deposited at a temperature of 650 to 700 C by reactive sputtering using selenium vapor and at least a second copper-indium-gallium alloy target having a different composition than the at least one first target. 16. A method of manufacturing a solar cell, comprising: providing a substrate and a first electrode located over the substrate, the first electrode comprising a first transition metal layer,reactively sputtering at least one p-type CIGS semiconductor absorber layer comprising a seed, bulk and top sublayers having a different composition from each other in a selenium containing atmosphere, wherein an atomic ratio in the atmosphere of selenium to metal comprising one of copper, indium and gallium is controlled to be 2 or less and wherein the top sublayer is reactively sputtered with a lower atomic selenium to metal ratio and a lower copper to metal ratio than the bulk sublayer;depositing an n-type semiconductor layer over the absorber layer; anddepositing a second electrode over the n-type semiconductor layer, wherein the seed sublayer has a higher ratio of Ga/(Ga+In) than the bulk sublayer,wherein the top sublayer has a lower ratio of Cu/(Ga+In) than the seed sublayer or the bulk sublayer, andwherein: the seed sublayer has a ratio of Ga/(Ga+In) of 0.4 to 0.6, and a ratio of Cu/(Ga+In) of 0.75 to 0.9; the bulk sublayer has a ratio of Ga/(Ga+In) of 0.2 to 0.3, and a ratio of Cu/(Ga+In) of 0.85 to 0.99; and the top sublayer has a ratio of Ga/(Ga+In) of 0.25 to 0.35, and a ratio of Cu/(Ga+In) of 0.05 to 0.3. 17. The method of claim 16, wherein the first transition metal layer comprises a sodium and oxygen containing molybdenum layer, wherein the first electrode further comprises a molybdenum barrier layer over the sodium and oxygen containing molybdenum layer. 18. The method of claim 16, wherein an atomic ratio in the atmosphere of selenium to metal is controlled to be above 5 during the reactive sputtering of the seed sublayer. 19. The method of claim 18, wherein the seed sublayer is deposited at a lower temperature than the bulk sublayer. 20. The method of claim 19, wherein the seed sublayer is deposited at a temperature of 450-500 C and the bulk sublayer is deposited at a temperature of 600-650 C. 21. The method of claim 16, further comprising performing a post deposition selenization anneal of the top sublayer. 22. The method of claim 21, wherein performing the post deposition selenization anneal of the top sublayer is performed while the substrate moves through a selenium atmosphere away from at least one sputtering target in a sputtering chamber in which the top sublayer was deposited. 23. The method of claim 16, wherein the p-type CIGS semiconductor absorber layer has a majority carrier concentration of about 1×1013 to about 1×1015 cm−3. 24. A solar cell, comprising: a substrate;a first electrode located over the substrate;at least one p-type CIGS semiconductor absorber layer containing sodium located over the first electrode;an n-type semiconductor layer located over the p-type semiconductor absorber layer; anda second electrode located over the n-type semiconductor layer;wherein p-type CIGS semiconductor absorber layer comprises a first copper indium gallium selenide sublayer adjacent to the first electrode, a second copper indium gallium selenide sublayer over the first sublayer, and a third copper indium gallium selenide sublayer over the second sublayer and adjacent to the n-type semiconductor layer; andthe third sublayer has a lower ratio of Cu/(Ga+In) than the first or the second sublayers, wherein: the first sublayer has a ratio of Ga/(Ga+In) of 0.4 to 0.6, and a ratio of Cu/(Ga+In) of 0.75 to 0.9; the second sublayer has a ratio of Ga/(Ga+In) of 0.2 to 0.3, and a ratio of Cu/(Ga+In) of 0.85 to 0.99; and the third sublayer has a ratio of Ga/(Ga+In) of 0.25 to 0.35, and a ratio of Cu/(Ga+In) of 0.05 to 0.3. 25. The solar cell of claim 24, wherein the solar cell comprises a flexible solar cell on a flexible substrate and the solar cell is formed in a shape of roofing shingle.
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