Method and apparatus for driving a power transistor gate
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H03K-017/16
H03K-017/14
H03K-017/567
H03K-017/0412
출원번호
US-0436740
(2012-10-31)
등록번호
US-10224923
(2019-03-05)
국제출원번호
PCT/IB2012/002653
(2012-10-31)
국제공개번호
WO2014/068352
(2014-05-08)
발명자
/ 주소
Sicard, Thierry
Perruchoud, Philippe
출원인 / 주소
NXP USA, Inc.
대리인 / 주소
Jacobsen, Charlene R.
인용정보
피인용 횟수 :
0인용 특허 :
9
초록▼
A gate drive circuit includes a first switch electrically coupled to a single-supply input voltage node, the first switch electrically coupling the voltage node with a first capacitor if switched on; a second switch electrically coupled to a ground node, the second switch electrically coupling the f
A gate drive circuit includes a first switch electrically coupled to a single-supply input voltage node, the first switch electrically coupling the voltage node with a first capacitor if switched on; a second switch electrically coupled to a ground node, the second switch electrically coupling the first capacitor with the ground node if switched on; and the first capacitor. A first capacitor lead of the first capacitor is electrically coupled to the first and second switches and a second capacitor lead of the first capacitor is arranged to connect with a power transistor gate.
대표청구항▼
1. A gate drive circuit comprising: a first switch controlled by a first switch signal, the first switch electrically coupled to a single-supply input voltage node, the first switch electrically coupling the voltage node with a first capacitor if switched on;a second switch controlled by a second sw
1. A gate drive circuit comprising: a first switch controlled by a first switch signal, the first switch electrically coupled to a single-supply input voltage node, the first switch electrically coupling the voltage node with a first capacitor if switched on;a second switch controlled by a second switch signal, the second switch electrically coupled to a ground node, the second switch electrically coupling the first capacitor with the ground node if switched on;the first capacitor, a first capacitor lead of the first capacitor electrically coupled to the first and second switches and a second capacitor lead of the first capacitor arranged to connect with a power transistor gate; anda Zener diode having a cathode electrically coupled to the first capacitor lead and an anode electrically coupled to the second capacitor lead, a maximum voltage across the first capacitor determined by a reverse breakdown voltage of the Zener diode. 2. The circuit of claim 1, wherein the circuit is an integrated circuit. 3. The circuit of claim 1 further comprising a second capacitor, the first capacitor lead of the second capacitor electrically coupled to the voltage node and the second lead of the second capacitor electrically coupled to the ground node. 4. The circuit of claim 1, wherein the capacitance of the first capacitor is at least approximately one-hundred times greater than a gate capacitance of the power transistor gate. 5. The circuit of claim 1, wherein the circuit is arranged to receive a control signal to control a gate drive output signal. 6. An IGBT module containing the circuit of claim 1, wherein: the IGBT module further comprises at least one IGBT transistor, andthe gate of the at least one IGBT transistor is electrically coupled to the second capacitor lead of the first capacitor. 7. The circuit of claim 1 further comprising a third switch electrically coupled to the second capacitor lead of the first capacitor and the ground node. 8. The circuit of claim 1 further comprising: a third switch electrically coupled to the second capacitor lead of the first capacitor and the ground node; anda diode connected in series with the third switch, the diode cathode electrical coupled to the third switch and the diode anode electrically connected to the second capacitor lead. 9. The circuit of claim 8, wherein the circuit further comprises a controller arranged to transmit a control signal to control at least one of the first, second, and third switches. 10. The circuit of claim 1, wherein the ground node is arranged to couple to an emitter of the power transistor. 11. A method of driving a gate of a power transistor comprising: charging a gate capacitance of the power transistor gate and a capacitor electrically connected in series with a power transistor gate, the charging by electrically coupling a first lead of the capacitor to a single supply voltage node using a first switch controlled by a first switch signal, the charging of the capacitor clamped by a Zener diode connected in parallel with the capacitor; anddischarging the capacitor during a transient change of the collector-emitter voltage of the power transistor, the discharging by electrically coupling the first lead of the capacitor to a ground node using a second switch controlled by a second switch signal, wherein the discharge is of sufficient magnitude to change a logical state of the power transistor gate. 12. The method of claim 11, wherein the capacitor has a capacitance of at least approximately one-hundred times greater than the gate capacitance. 13. The method of claim 11, wherein the capacitor has a capacitance of approximately 10 μF and the gate capacitance is approximately 100 nF. 14. The method of claim 11, wherein discharging the capacitor comprises discharging the capacitor during a positive transient change of the collector-emitter voltage of the power transistor. 15. The method of claim 11, wherein the transient change of the collector-emitter voltage is at least 1 volt per nanosecond. 16. The method of claim 11, wherein charging comprises charging substantially concurrently the gate capacitance and the capacitor. 17. The method of claim 11, wherein the power transistor is an IGBT. 18. The method of claim 11 further comprising: blocking current flowing from ground when a negative voltage is applied to the power transistor gate, the blocking provided by a diode having an anode connected to the power transistor gate and a cathode coupled to ground via a switch. 19. The method of claim 11, wherein an emitter of the power transistor is coupled to the ground node.
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이 특허에 인용된 특허 (9)
Miettinen,Erkki, Control circuit for semiconductor component.
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