최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0614973 (2017-06-06) |
등록번호 | US-10230377 (2019-03-12) |
발명자 / 주소 |
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출원인 / 주소 |
|
대리인 / 주소 |
|
인용정보 | 피인용 횟수 : 0 인용 특허 : 587 |
An exclusive-or circuit includes a pass gate controlled by a second input node. The pass gate is connected to pass through a version of a logic state present at a first input node to an output node when so controlled. A transmission gate is controlled by the first input node. The transmission gate i
An exclusive-or circuit includes a pass gate controlled by a second input node. The pass gate is connected to pass through a version of a logic state present at a first input node to an output node when so controlled. A transmission gate is controlled by the first input node. The transmission gate is connected to pass through a version of the logic state present at the second input node to the output node when so controlled. Pullup logic is controlled by both the first and second input nodes. The pullup logic is connected to drive the output node low when both the first and second input nodes are high. An exclusive-nor circuit is defined similar to the exclusive-or circuit, except that the pullup logic is replaced by pulldown logic which is connected to drive the output node high when both the first and second input nodes are high.
1. An exclusive-or circuit, comprising: a first conductive structure including a portion that forms a gate electrode of a first PMOS transistor and a portion that forms a gate electrode of a first NMOS transistor, the first conductive structure extending lengthwise in a single direction;a second con
1. An exclusive-or circuit, comprising: a first conductive structure including a portion that forms a gate electrode of a first PMOS transistor and a portion that forms a gate electrode of a first NMOS transistor, the first conductive structure extending lengthwise in a single direction;a second conductive structure including a portion that forms a gate electrode of a second PMOS transistor and a portion that forms a gate electrode of a second NMOS transistor, the second conductive structure extending lengthwise in the single direction;a third conductive structure including a portion that forms a gate electrode of a third PMOS transistor and a portion that forms a gate electrode of a third NMOS transistor, the third conductive structure extending lengthwise in the single direction;a fourth conductive structure including a portion that forms a gate electrode of a fourth PMOS transistor, the fourth conductive structure extending lengthwise in the single direction;a fifth conductive structure including a portion that forms a gate electrode of a fifth PMOS transistor and a portion that forms a gate electrode of a fourth NMOS transistor, the fifth conductive structure extending lengthwise in the single direction; anda sixth conductive structure including a portion that forms a gate electrode of a sixth PMOS transistor and a portion that forms a gate electrode of a fifth NMOS transistor, the sixth conductive structure extending lengthwise in the single direction,wherein the first PMOS transistor is positioned next to the second PMOS transistor, and wherein the first PMOS transistor and the second PMOS transistor share a first diffusion region,wherein the second PMOS transistor is positioned next to the third PMOS transistor, and wherein the second PMOS transistor and the third PMOS transistor share a second diffusion region,wherein the third PMOS transistor is positioned next to the fourth PMOS transistor, and wherein the third PMOS transistor and the fourth PMOS transistor share a third diffusion region,wherein the fourth PMOS transistor is positioned next to the fifth PMOS transistor, and wherein the fourth PMOS transistor and the fifth PMOS transistor share a fourth diffusion region,wherein the fifth PMOS transistor is positioned next to the sixth PMOS transistor, and wherein the fifth PMOS transistor and the sixth PMOS transistor share a fifth diffusion region,wherein the first NMOS transistor is positioned next to the second NMOS transistor, and wherein the first NMOS transistor and the second NMOS transistor share a sixth diffusion region,wherein the second NMOS transistor is positioned next to the third NMOS transistor, and wherein the second NMOS transistor and the third NMOS transistor share a seventh diffusion region, andwherein the fourth NMOS transistor is positioned next to the fifth NMOS transistor, and wherein the fourth NMOS transistor and the fifth NMOS transistor share an eighth diffusion region. 2. An exclusive-or circuit as recited in claim 1, wherein the first PMOS transistor and the first NMOS transistor form a first inverter, wherein both the first diffusion region and the sixth diffusion region are electrically connected to an output of the first inverter, wherein the gate electrodes of both the first PMOS transistor and the first NMOS transistor are electrically connected to a first input node of the exclusive-or circuit. 3. An exclusive-or circuit as recited in claim 2, wherein the output of the first inverter is electrically connected to gate electrodes of both the third PMOS transistor and the third NMOS transistor. 4. An exclusive-or circuit as recited in claim 3, wherein the fourth NMOS transistor is formed in part by a ninth diffusion region. 5. An exclusive-or circuit as recited in claim 4, wherein the fifth PMOS transistor and the fourth NMOS transistor form a second inverter, wherein both the fourth diffusion region and the ninth diffusion region are electrically connected to an output of the second inverter, wherein the gate electrodes of both the fifth PMOS transistor and the fourth NMOS transistor are electrically connected to a second input node of the exclusive-or circuit. 6. An exclusive-or circuit as recited in claim 5, wherein the output of the second inverter is electrically connected to gate electrodes of both the second PMOS transistor and the second NMOS transistor. 7. An exclusive-or circuit as recited in claim 6, wherein the third NMOS transistor is formed in part by a tenth diffusion region, wherein the output of the second inverter is electrically connected to tenth diffusion region. 8. An exclusive-or circuit as recited in claim 7, wherein the sixth PMOS transistor and the fifth NMOS transistor form a third inverter. 9. An exclusive-or circuit as recited in claim 8, wherein the sixth PMOS transistor is formed in part by an eleventh diffusion region, wherein the fifth NMOS transistor is formed in part by a twelfth diffusion region, wherein both the eleventh diffusion region and the twelfth diffusion region are electrically connected to an output of the third inverter, wherein the output of the third inverter is electrically connected to an output node of the exclusive-or circuit. 10. An exclusive-or circuit as recited in claim 9, wherein the gate electrodes of both the sixth PMOS transistor and the fifth NMOS transistor are electrically connected to both the third diffusion region and the seventh diffusion region. 11. An exclusive-or circuit as recited in claim 10, wherein both the first diffusion region and the fifth diffusion region are electrically connected to a power supply node. 12. An exclusive-or circuit as recited in claim 11, wherein the first NMOS transistor is formed in part by a thirteenth diffusion region, wherein both the thirteenth diffusion region and the eighth diffusion region are electrically connected to a reference ground potential node. 13. An exclusive-or circuit as recited in claim 12, wherein the first input node of the exclusive-or circuit is electrically connected to the gate electrode of the fourth PMOS transistor. 14. An exclusive-or circuit as recited in claim 7, wherein the tenth diffusion region is separated from the ninth diffusion. 15. An exclusive-or circuit as recited in claim 14, wherein the tenth diffusion region is electrically connected to the ninth diffusion through an interconnect structure located within a first interconnect level above a gate electrode level. 16. An exclusive-or circuit as recited in claim 7, wherein the fourth conductive structure extends lengthwise along a line that extends between the tenth diffusion region and the ninth diffusion region. 17. An exclusive-or circuit as recited in claim 1, wherein the single direction is a first direction, each of the first, second, third, fourth, fifth, and sixth conductive structures are positioned in accordance with a fixed pitch as measured in a second direction perpendicular to the first direction. 18. An exclusive-or circuit as recited in claim 1, wherein the first, second, third, fourth, fifth, and sixth PMOS transistors are collectively separated from the first, second, third, fourth, and fifth NMOS transistors by an inactive region that does not include a transistor source region or a transistor drain region.
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