Managing an effective address table in a multi-slice processor
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-009/32
G06F-009/34
G06F-009/35
G06F-012/02
G06F-013/36
G06F-012/1009
출원번호
US-0220798
(2016-07-27)
등록번호
US-10241905
(2019-03-26)
발명자
/ 주소
Giri, Akash V.
Levitan, David S.
Patel, Mehul
Van Norstrand, Jr., Albert J.
출원인 / 주소
INTERNATIONAL BUSINESS MACHINES CORPORATION
대리인 / 주소
Rau, Nathan M.
인용정보
피인용 횟수 :
0인용 특허 :
19
초록▼
Methods and apparatus for managing an effective address table (EAT) in a multi-slice processor including receiving, from an instruction sequence unit, a next-to-complete instruction tag (ITAG); obtaining, from the EAT, a first ITAG from a tail-plus-one EAT row, wherein the EAT comprises a tail EAT r
Methods and apparatus for managing an effective address table (EAT) in a multi-slice processor including receiving, from an instruction sequence unit, a next-to-complete instruction tag (ITAG); obtaining, from the EAT, a first ITAG from a tail-plus-one EAT row, wherein the EAT comprises a tail EAT row that precedes the tail-plus-one EAT row; determining, based on a comparison of the next-to-complete ITAG and the first ITAG, that the tail EAT row has completed; and retiring the tail EAT row based on the determination.
대표청구항▼
1. A method of managing an effective address table (EAT), the method comprising: receiving, by EAT management logic of an instruction fetch unit from an instruction sequence unit, a next-to-complete instruction tag (ITAG);obtaining, from the EAT, a first ITAG from a tail-plus-one EAT row, wherein th
1. A method of managing an effective address table (EAT), the method comprising: receiving, by EAT management logic of an instruction fetch unit from an instruction sequence unit, a next-to-complete instruction tag (ITAG);obtaining, from the EAT, a first ITAG from a tail-plus-one EAT row, wherein the EAT comprises a tail EAT row that precedes the tail-plus-one EAT row; and wherein each EAT row comprises a starting effective address, an ending effective address, and a first ITAG in a range of ITAG assigned to internal operations generated from processor instructions stored at a range of effective addresses defined by the starting effective address and the ending effective address;determining, based on a comparison of the next-to-complete ITAG and the first ITAG, that the tail EAT row has completed; andretiring the tail EAT row based on the determination, thereby retiring one or more effective address of the tail EAT row, wherein retiring the tail EAT row further comprises freeing a range of ITAGs associated with the tail EAT row for reassignment to newly decoded instructions. 2. The method of claim 1 wherein determining, based on a comparison of the next-to-complete ITAG and the first ITAG, that the tail EAT row has completed comprises: determining that the next-to-complete ITAG is greater than or equal to the first ITAG. 3. The method of claim 2 wherein the first ITAG is a first in a range of ITAGs associated with the tail-plus-one EAT row, and wherein the range of ITAGs associated with the tail-plus-one EAT row does not comprise the next-to-complete ITAG. 4. The method of claim 1 further comprising: advancing a tail pointer to point to the tail-plus-one EAT row. 5. The method of claim 4 further comprising: receiving an additional next-to-complete ITAG;determining that a tail-plus-two EAT row comprises a first ITAG that is greater than the additional next-to-complete ITAG; anddelaying retirement of the tail-plus-one EAT row. 6. The method of claim 1 wherein retiring the tail EAT row comprises: updating a come from address register. 7. The method of claim 1 wherein receiving the next-to-complete ITAG indicates that all ITAGs less than the next-to-complete ITAG have completed.
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