Metal resistors having nitridized metal surface layers with different nitrogen content
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-049/02
H01L-021/62
H01L-027/01
H01L-021/66
H01L-021/02
H01L-023/522
H01L-021/768
출원번호
US-0935942
(2018-03-26)
등록번호
US-10249703
(2019-04-02)
발명자
/ 주소
Edelstein, Daniel C.
Yang, Chih-Chao
출원인 / 주소
International Business Machines Corporation
대리인 / 주소
Scully, Scott, Murphy & Presser, P.C.
인용정보
피인용 횟수 :
0인용 특허 :
11
초록▼
A semiconductor structure containing at least two metal resistor structures having different amounts of nitrogen on the resistor surface is provided. The resulted resistances (and hence resistivity) of the two metal resistors can be either the same or different. The semiconductor structure may inclu
A semiconductor structure containing at least two metal resistor structures having different amounts of nitrogen on the resistor surface is provided. The resulted resistances (and hence resistivity) of the two metal resistors can be either the same or different. The semiconductor structure may include a first metal resistor structure located on a portion of a dielectric-containing substrate. The first metal resistor structure includes, from bottom to top, a first metal layer portion and a first nitridized metal surface layer having a first nitrogen content. The semiconductor structure further includes a second metal resistor structure located on a second portion of the dielectric-containing substrate and spaced apart from the first metal resistor structure. The second metal resistor structure includes, from bottom to top, a second metal layer portion and a second nitridized metal surface layer having a second nitrogen content that differs from the first nitrogen content.
대표청구항▼
1. A method of forming a semiconductor structure, said method comprising: providing a dielectric-containing substrate comprising at least an interconnect dielectric material layer;forming a first metal layer portion on a first portion of a topmost surface of said interconnect dielectric material lay
1. A method of forming a semiconductor structure, said method comprising: providing a dielectric-containing substrate comprising at least an interconnect dielectric material layer;forming a first metal layer portion on a first portion of a topmost surface of said interconnect dielectric material layer, and a second metal layer portion on a second portion of said topmost surface of said interconnect dielectric material layer;performing a first nitridation process to provide a first nitridized metal surface layer having a first nitrogen content within said first metal layer portion, wherein said first metal layer portion and said first nitridized metal surface layer provide a first metal resistor structure; andperforming a second nitridation process to provide a second nitridized metal surface layer having a second nitrogen content that differs from said first nitrogen content within said second metal layer portion, wherein said second metal layer portion and said second nitridized metal surface layer provide a second metal resistor structure. 2. The method of claim 1, wherein said providing said dielectric-containing substrate comprises: forming a base dielectric capping layer on a surface of a base interconnect dielectric material layer, said base interconnect dielectric material layer containing at least one conductive region embedded therein; andforming said interconnect dielectric material layer on said base dielectric capping layer. 3. The method of claim 1, wherein at least one of said first nitridation process and said second nitridation process comprises a thermal nitridation process, wherein said thermal nitridation process is performed at a temperature from 50° C. to 450° C. in a nitrogen-containing ambient, wherein said nitrogen-containing ambient used in said first nitridation process comprises a different nitrogen content than said nitrogen-containing ambient used in said second nitridation process. 4. The method of claim 1, wherein at least one of said first nitridation process and said second nitridation process comprises a plasma nitridation process, wherein said plasma nitridation process is performed at a temperature from 50° C. to 450° C. in a nitrogen-containing ambient, wherein said nitrogen-containing ambient used in said first nitridation process comprises a different nitrogen content than said nitrogen-containing ambient used in said second nitridation process. 5. The method of claim 1, wherein at least one of said first nitrogen content and said second nitrogen content is 10 atomic percent or greater. 6. The method of claim 1, further comprising measuring resistance of both said first metal layer portion and said second metal layer portion prior to performing said first and second nitridation processes, wherein said resistance provides information on a content of nitrogen to be used during said first and second nitridation processes. 7. The method of claim 1, further comprising forming a dielectric capping layer on said first metal resistor structure and said second metal resistor structure. 8. The method of claim 1, further comprising measuring resistance of said first metal resistor structure prior to said performing said second nitridation process. 9. The method of claim 8, further comprising performing, after said measuring of said resistance, a trimming process. 10. The method of claim 1, further comprising measuring resistance of said second metal resistor structure after said performing said second nitridation process. 11. The method of claim 10, further comprising performing, after said measuring of said resistance, a trimming process. 12. The method of claim 1, further comprising forming a contact structure surrounding said first and second metal resistor structures, wherein said contact structure includes metal contacts extending to a topmost surface of each of said first metal resistor structure and said second metal resistor structure. 13. The method of claim 1, wherein said first metal layer portion is spaced apart from said second metal layer portion. 14. The method of claim 7, wherein said dielectric capping layer is a continuous layer that is present on a topmost surface of said first metal layer portion, a sidewall surface of said first metal layer portion, a third portion of said topmost surface of said interconnect dielectric material, a sidewall surface of said second metal layer portion, and a topmost surface of said second metal layer portion. 15. The method of claim 1, wherein said first metal layer portion has a topmost surface that is coplanar with a topmost surface of said second metal layer portion. 16. The method of claim 1, wherein said forming said first metal layer portion and said second metal layer portion comprises: forming a continuous metal layer on said interconnect dielectric material layer; andpatterning said continuous material layer. 17. The method of claim 16, wherein said continuous metal layer is selected from at least one of TaN, Ta, TiN, Ti, RuN, Ru, CoN, Co, WN, W, TaRuN, and TaRu. 18. The method of claim 3, wherein said thermal nitridation process is performed using an electrical bias of less than 200 W. 19. The method of claim 4, wherein said plasma nitridation process is performed using an electrical bias of greater than 200 W. 20. The method of claim 1, wherein at least one of said first nitrogen content and said second nitrogen content is less than 10 atomic percent.
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이 특허에 인용된 특허 (11)
Yang, Chih-Chao; Edelstein, Daniel C.; Molis, Steven E., Enhanced diffusion barrier for interconnect structures.
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