A drive circuit having asymmetrical drivers. In an embodiment, a brushless DC motor may be driven by a drive circuit having three high-side MOSFETs and three low-side MOSFETs. A driver controller turns the MOSFETs on and off according to a drive algorithm such that phase currents are injected into m
A drive circuit having asymmetrical drivers. In an embodiment, a brushless DC motor may be driven by a drive circuit having three high-side MOSFETs and three low-side MOSFETs. A driver controller turns the MOSFETs on and off according to a drive algorithm such that phase currents are injected into motor coils to be driven. The high-side MOSFETs may be sized differently than the low-side MOSFETs. As such, when a MacDonald waveform (or similar drive algorithm) is used to drive the phases of the motor, less power may be required during disk spin-up because the MOSFETs that are on more (e.g., the low-side MOSFETs with a MacDonald waveform) may be sized larger than the MOSFETs that are on less (e.g., the high-side MOSFETs). In this manner, less power is dissipated in the larger size MOSFETs that are on more than the others.
대표청구항▼
1. A drive circuit, comprising: a bridge circuit including a first drive circuit including a first transistor having a first on resistance and a second drive circuit including a second transistor having a second on resistance that is greater than the first on resistance, the first and second transis
1. A drive circuit, comprising: a bridge circuit including a first drive circuit including a first transistor having a first on resistance and a second drive circuit including a second transistor having a second on resistance that is greater than the first on resistance, the first and second transistors being coupled in series between a supply voltage node and a reference voltage node and the first and second drive circuits configured to be driven in a pulse-width modulation mode by an asymmetrical drive algorithm to control the first and second transistors during a phase drive cycle to activate the first transistor for a longer portion of the phase drive cycle than the second transistor to reduce a power loss in the first and second transistors relative to a power loss in the first and second transistors when the first and second on resistances have the same value. 2. The drive circuit of claim 1 where each of the first and second drive circuits comprises a respective transistor. 3. The drive circuit of claim 2, wherein each transistor comprises a MOSFET transistor. 4. The drive circuit of claim 3, wherein each of the transistors has a channel with a corresponding width-to-length ratio to provide the on resistance having a desired value. 5. The drive circuit of claim 1, wherein: the first drive circuit comprises one of a high side and a low side driver; andthe second drive circuit comprises the other of the high side and low side driver. 6. A controller, comprising: a disk-drive controller operable to control operation of a disk drive including a motor; anda drive circuit coupled to the disk-drive controller and, under control of the disk-drive controller, operable to control operation of the motor in the disk drive, the drive circuit including a first drive component having a first value of a drive characteristic and a second drive component having a second value of the drive characteristic, the second value being different than the first value and the first and second values determining a power consumption of the first and second drive components, respectively, and the first and second drive components being coupled in series between a supply voltage node and a reference voltage node; andwherein the disk-drive controller is operable in a pulse-width modulation mode of operation to asymmetrically activate the first and second drive components so that one of the first and second drive components is activated for a longer duration of a phase drive cycle than a duration for which the other one of the first and second drive components is activated, the asymmetrical activation causing a power loss of the first drive component to be different than a power loss of the second drive component, and the first and second drive characteristics having values that reduce a total power loss of the first and second drive components relative to a total power loss in the first and second drive components when the first and second drive characteristics have the same value. 7. The controller of claim 6, further comprising one of a first integrated circuit die including the disk-drive controller coupled to a second integrated circuit die including the drive circuit and a single integrated circuit die including both the disk-drive controller and the drive circuit. 8. The controller of claim 6, wherein: the first drive component comprises one of a high side and a low side driver; andthe second drive component comprises the other of the high side and low side driver. 9. The controller of claim 8, wherein each of the first and second drive components comprises a respective transistor. 10. The controller of claim 9, wherein the drive characteristic of each transistor corresponds to an ON resistance the transistor, and wherein the transistor that is activated for the longer duration of the phase drive cycle has the smaller ON resistance. 11. The controller of claim 9, wherein the drive characteristic of each transistor corresponds to a size of the transistor, and wherein the transistor that is activated for the longer duration of the phase drive cycle has the larger size. 12. The controller of claim 11, wherein the size of each transistor is defined by a channel length and a channel width of the transistor. 13. The controller of claim 12, wherein each of the transistors is a MOSFET transistor with a channel length and width that defines a corresponding width-to-length ratio so the MOSFET transistor has a resistance RDSON of a desired value. 14. The controller of claim 12 further comprising the disk drive and wherein the motor comprises a three-phase, brushless direct-current motor. 15. The controller of claim 14 further: a memory coupled to the drive circuit and operable to store a drive algorithm; andwherein the disk-drive controller is coupled to the memory and configured to control the drive circuit according to the stored drive algorithm to asymmetrically activate the first and second drive components. 16. A method, comprising: turning on a first drive circuit having a first level of a drive characteristic for a first portion of a drive period of a pulse width modulation mode of operation;turning off a second drive circuit having a second level of the drive characteristic for the first portion of the drive period in the pulse width modulation mode of operation, wherein the second level is not equal to the first level;turning on the second drive circuit for a second portion of the drive period in the pulse width modulation mode of operation;turning off the first drive circuit for the second portion of the drive period in the pulse width modulation mode of operation;wherein the second portion is not equal to the first portion and durations of the first and second portions are defined by an asymmetrical drive algorithm that controls the first and second drive circuits in the pulse width modulation mode of operation to asymmetrically activate the first and second drive circuits to provide a first power consumption in the first drive circuit that is different than a second power consumption in the second drive circuit, a total power consumption that is equal to the sum of the first and second power consumptions being less than a total power consumption in the first and second drive circuits when the drive characteristics of the first and second drive circuits have the same value. 17. The method of claim 16, wherein the asymmetrical drive algorithm comprises a MacDonald waveform. 18. The method of claim 16, wherein the drive characteristic comprises an ON resistance of a transistor. 19. The method of claim 18, wherein the drive characteristic comprises a size of a transistor defined by a channel length and a channel width of the transistor. 20. The method of claim 16 further comprising applying the asymmetrical drive algorithm to turn on and off the first and second drive circuits includes applying the asymmetrical drive algorithm during a spin up period of a disk being rotated by a motor being controlled by the asymmetrical drive algorithm.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (47)
Abu Qahouq, Jaber; Huang, Lilly, Adaptive controller with mode tracking and parametric estimation for digital power converters.
Mller Rolf (St. Georgen DEX), Collectorless direct current motor, driver circuit for a drive and method of operating a collectorless direct current mo.
Williams Richard K. (Cupertino CA) Chang Allen A. (Milpitas CA) Concklin Barry J. (San Jose CA), Disconnect switch circuit to power head retract in hard disk drive memories.
Bennett, George J.; Ryan, Robert P., Disk drive comprising a pulse width modulated demand limit circuit for enhancing power management during spin-down.
Galbiati Ezio,ITX ; Boscolo Michele,ITX ; Viti Marco,ITX, Method of PWM driving a brushless motor with digitally stored voltage profiles with reduced losses.
El Sherif,Alaa Y.; Plutowski,Eugene F.; Ziemer,Kevin W., Rejection of power supply variations for gain error cancellation in pulse-width-modulated motor controllers.
Leong,Foo Leng; Chui,Siew Yong; Teoh,Cheng Yong; Rana,Sakti Pada, System and method for detecting back electromotive force with automatic pole calibration.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.