Method and apparatus for adapting a variable impedance network
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H03H-007/38
H03H-007/40
H03H-005/12
H03H-007/00
H03K-017/56
출원번호
US-0673613
(2017-08-10)
등록번호
US-10263595
(2019-04-16)
발명자
/ 주소
Manssen, Keith
Greene, Matthew Russell
출원인 / 주소
BLACKBERRY LIMITED
대리인 / 주소
Guntin & Gust, PLC
인용정보
피인용 횟수 :
0인용 특허 :
281
초록▼
The present disclosure may include, for example, a tunable capacitor having a decoder for generating a plurality of control signals, and an array of tunable switched capacitors comprising a plurality of fixed capacitors coupled to a plurality of switches. The plurality of switches can be controlled
The present disclosure may include, for example, a tunable capacitor having a decoder for generating a plurality of control signals, and an array of tunable switched capacitors comprising a plurality of fixed capacitors coupled to a plurality of switches. The plurality of switches can be controlled by the plurality of control signals to manage a tunable range of reactance of the array of tunable switched capacitors. Additionally, the array of tunable switched capacitors is adapted to have non-uniform quality (Q) factors. Additional embodiments are disclosed.
대표청구항▼
1. A device comprising: a tunable array of switched capacitors comprising a plurality of capacitors coupled to a plurality of switches, each of the plurality of capacitors having a fixed capacitance value, each of the plurality of switches having a resistance associated therewith;wherein the capacit
1. A device comprising: a tunable array of switched capacitors comprising a plurality of capacitors coupled to a plurality of switches, each of the plurality of capacitors having a fixed capacitance value, each of the plurality of switches having a resistance associated therewith;wherein the capacitance values of the plurality of capacitors comprise a non-binary array, andwherein the array of switched capacitors is adapted to have non-uniform quality (Q) factors. 2. The device of claim 1, wherein each combination of a capacitor of the plurality of capacitors and a switch of the plurality of switches has a quality (Q) factor, and the array corresponds to a plurality of combinations having different Q factors. 3. The device of claim 1, wherein a first capacitor and a second capacitor of the array of switched capacitors each have a capacitance value equal to a largest capacitance value of the non-binary array. 4. The device of claim 1, wherein the device comprises a matching network operating in a frequency range having a low-frequency portion and a high-frequency portion,wherein a first capacitor having a capacitance value equal to a largest capacitance value of the array is connected to a first resistance of a first switch to maintain a target quality (Q) factor for the matching network while operating in the low-frequency portion of the frequency range, and is not connected to the first resistance while the matching network is operating in the high-frequency portion of the frequency range. 5. The device of claim 1, wherein at least a portion of the array of switched capacitors is contained on a die. 6. The device of claim 1, wherein the resistance associated with at least one switch of the plurality of switches comprises a parasitic resistance. 7. The device of claim 1, wherein at least one switch of the plurality of switches comprises a semiconductor switch. 8. The device of claim 1, wherein at least one switch of the plurality of switches comprises a micro-electro-mechanical systems (MEMS) switch. 9. A device comprising: a tunable array of switched capacitors comprising a plurality of capacitors coupled to a plurality of switches, each of the plurality of capacitors having a fixed capacitance value, each of the plurality of switches having a resistance associated therewith,wherein the array of switched capacitors is adapted to have non-uniform quality (Q) factors, the array of switched capacitors thereby adapted to maintain a Q factor for the array over a predetermined portion of a frequency range of the device. 10. The device of claim 9, wherein each combination of a capacitor of the plurality of capacitors and a switch of the plurality of switches has a Q factor, and the array corresponds to a plurality of combinations having different Q factors. 11. The device of claim 9, wherein the device comprises a matching network operating in the frequency range, the frequency range having a low-frequency portion and a high-frequency portion,wherein a first capacitor having a capacitance value equal to a largest capacitance value of the array is connected to a first resistance of a first switch to maintain a target quality (Q) factor for the matching network while operating in the low-frequency portion of the frequency range, and is not connected to the first resistance while the matching network is operating in the high-frequency portion of the frequency range. 12. The device of claim 9, wherein at least a portion of the array of switched capacitors is contained on a die. 13. The device of claim 9, wherein the resistance associated with at least one switch of the plurality of switches comprises a parasitic resistance. 14. The device of claim 9, wherein at least one switch of the plurality of switches comprises a semiconductor switch. 15. The device of claim 9, wherein at least one switch of the plurality of switches comprises a micro-electro-mechanical systems (MEMS) switch. 16. A device comprising: a tunable array of switched reactive elements comprising a plurality of reactive elements coupled to a plurality of switches, each of the plurality of reactive elements having a fixed reactance value, each of the plurality of switches having a resistance associated therewith,wherein the array of switched reactive elements is adapted to have non-uniform quality (Q) factors, the array of switched reactive elements thereby adapted to maintain a Q factor for the array over a predetermined portion of a frequency range of the device. 17. The device of claim 16, wherein at least one switch of the plurality of switches comprises a semiconductor switch. 18. The device of claim 16, wherein at least one switch of the plurality of switches comprises a micro-electro-mechanical systems (MEMS) switch. 19. The device of claim 16, wherein the array comprises a plurality of capacitors coupled to the plurality of switches, wherein each of the plurality of switches has a parasitic capacitance, and wherein the resistance associated with at least one switch of the plurality of switches comprises a parasitic resistance. 20. The device of claim 19, wherein the device comprises a matching network operating in the frequency range, the frequency range having a low-frequency portion and a high-frequency portion,wherein a first capacitor having a capacitance value equal to a largest capacitance value of the plurality of capacitors is connected to a first resistance of a first switch to maintain a target Q factor for the matching network while operating in the low-frequency portion of the frequency range, and is not connected to the first resistance while the matching network is operating in the high-frequency portion of the frequency range.
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