In modern wireless communication systems such as wide-band code division multiple access (WCDMA), orthogonal frequency division multiple (OFDM), and so on, modulated signals have a high peak-to-average power ratio (PAPR). Thus, power amplifiers (PAs) in repeaters and base stations should be operated...
In modern wireless communication systems such as wide-band code division multiple access (WCDMA), orthogonal frequency division multiple (OFDM), and so on, modulated signals have a high peak-to-average power ratio (PAPR). Thus, power amplifiers (PAs) in repeaters and base stations should be operated at a large back-off power (BOP) from the saturation power to achieve proper linearity but result in poor efficiency. Since PAs consume a majority of the power in the wireless communication transmitter and have a close relation to the thermal problem, it is very critical to improve the efficiency of PA circuits while still satisfying the linearity requirements for the given system. However, it is very difficult to achieve high linearity and high efficiency in the PA design due to their trade-off relation. Currently, PAs have been designed to achieve high efficiency by various switching-mode PAs (SMPAs), envelope elimination and restoration (EER), envelope tracking (ET), and then terrible linearity of efficiency-boosting techniques has been improved by various predistortion methods such as analog or digital predistortion techniques. Among high-efficiency PA configurations, various SMPAs such as class-D, class-E, inverse class-E, class-F, inverse class-F, and so on are the most popular structure. The operation of the SMPAs is based on the minimization of the power dissipated in the transistor at the switching instant and the significant termination of high-order harmonic power levels. If the transistor behaves as an ideal switch, theoretical drain efficiency of 100% can be achieved by reducing the overlap between drain voltage and current waveforms across the transistor. In practice, the maximum efficient operation is limited since the transistor can be no longer regarded as an ideal switch because of the internal parasitic components of the packaged transistor. First, these parasitic components should be identified by simple device characterization. Next, they must be considered in the SMPA design to achieve high output power and high efficiency by reducing their effects at the switching instants. In Chapter 2, various highly efficient SMPAs with simple parasitic compensation elements are presented and validated experimentally. In the class-E PA design, the parasitic output capacitance of the packaged transistor is used as the shunt capacitor in the class-E topology but nonlinear capacitance-voltage characteristics of large parasitic output capacitance is reduced by the shunt inductor. Additionally, parasitic resistance of the device and inductance of the package are compensated for by the series capacitor. Moreover, the output matching circuit using λ/4-length open stubs and series transmission lines (TLs) is employed to give an open circuit for all harmonics. In the inverse class-E PA design, the parasitic inductance and large output capacitance of the packaged GaN HEMT are used as the series inductance and compensated by a shunt inductor, respectively. The composite right/left-handed TL (CRLH-TL) is used as a harmonic trap to provide a short circuit for all harmonics. To design highly efficient class-F PA, the compensation elements with the series capacitor and shunt inductor are inserted in front of the harmonic control network since the harmonic control should be performed after the current source by compensating for the internal parasitic components of the packaged transistor. The CRLH-TL with an additional λ/4-length TL is used as a harmonic tuner, which provides a short for even harmonics and an open for odd harmonics. PAs should provide highly efficient operation at a large BOP due to modulated signals with high PAPR. Therefore, Doherty PAs (DPAs) are the most attractable configuration to deliver high efficiency at a large BOP. In practice, DPA can？t deliver high efficiency at a large BOP and full output power due to soft turn-on effects of the transistors. In order to optimize the efficiency of DPA, various techniques such as uneven power drive, envelope tracking bias control, and high-efficiency SMPAs have been employed. However, they have been optimized at 6-dB BOP and are insufficient to provide high efficiency over 9-dB BOP. Also, the asymmetrical, N-way or multistage Doherty configurations can provide a wide efficiency range, but they result in low power gain and lay a burden on the drive amplifier due to N-way power splitter as well as complicated and less cost-effective design. In spite of the high-efficiency performance at a large BOP, DPAs show inherent poor linearity. Chapter 3 introduces various novel designs and applications of DPAs. In terms of efficiency optimization at a large BOP, asymmetrical DPA considering soft turn-on effects, unequal-cells-based DPA using uneven saturation power, and highly efficient DPA employing class-E topology are presented. For the linearity optimization, power-tracking DPAs using derivative superposition techniques and N-way DPAs with predistortion driver are shown. In the other word, the nonlinearity of the DPA is used as predistortion circuit for high-power amplifier linearization. In addition, a new distributed DPA is presented for wideband performance. For the linearity improvement of PAs, various linearization techniques have been widely researched and developed. Among various linearization techniques, feedfoward techniques provide excellent linearity improvement. But, they have not paid much attention to PA designers due to inherent efficiency-decreasing nature as well as bulky size and circuit complexity. Digital predistortion (DPD) approaches become a very promising method due to their high intermodulation (IM) suppression, but is complicated and implemented at the base band level. In other hand, analog predistortion (APD) techniques work at the RF with the advantage of simple circuitry and low cost. However, APDs haven't delivered the sufficient linearity improvement for modulated signals with wide signal bandwidth. One rea
In modern wireless communication systems such as wide-band code division multiple access (WCDMA), orthogonal frequency division multiple (OFDM), and so on, modulated signals have a high peak-to-average power ratio (PAPR). Thus, power amplifiers (PAs) in repeaters and base stations should be operated at a large back-off power (BOP) from the saturation power to achieve proper linearity but result in poor efficiency. Since PAs consume a majority of the power in the wireless communication transmitter and have a close relation to the thermal problem, it is very critical to improve the efficiency of PA circuits while still satisfying the linearity requirements for the given system. However, it is very difficult to achieve high linearity and high efficiency in the PA design due to their trade-off relation. Currently, PAs have been designed to achieve high efficiency by various switching-mode PAs (SMPAs), envelope elimination and restoration (EER), envelope tracking (ET), and then terrible linearity of efficiency-boosting techniques has been improved by various predistortion methods such as analog or digital predistortion techniques. Among high-efficiency PA configurations, various SMPAs such as class-D, class-E, inverse class-E, class-F, inverse class-F, and so on are the most popular structure. The operation of the SMPAs is based on the minimization of the power dissipated in the transistor at the switching instant and the significant termination of high-order harmonic power levels. If the transistor behaves as an ideal switch, theoretical drain efficiency of 100% can be achieved by reducing the overlap between drain voltage and current waveforms across the transistor. In practice, the maximum efficient operation is limited since the transistor can be no longer regarded as an ideal switch because of the internal parasitic components of the packaged transistor. First, these parasitic components should be identified by simple device characterization. Next, they must be considered in the SMPA design to achieve high output power and high efficiency by reducing their effects at the switching instants. In Chapter 2, various highly efficient SMPAs with simple parasitic compensation elements are presented and validated experimentally. In the class-E PA design, the parasitic output capacitance of the packaged transistor is used as the shunt capacitor in the class-E topology but nonlinear capacitance-voltage characteristics of large parasitic output capacitance is reduced by the shunt inductor. Additionally, parasitic resistance of the device and inductance of the package are compensated for by the series capacitor. Moreover, the output matching circuit using λ/4-length open stubs and series transmission lines (TLs) is employed to give an open circuit for all harmonics. In the inverse class-E PA design, the parasitic inductance and large output capacitance of the packaged GaN HEMT are used as the series inductance and compensated by a shunt inductor, respectively. The composite right/left-handed TL (CRLH-TL) is used as a harmonic trap to provide a short circuit for all harmonics. To design highly efficient class-F PA, the compensation elements with the series capacitor and shunt inductor are inserted in front of the harmonic control network since the harmonic control should be performed after the current source by compensating for the internal parasitic components of the packaged transistor. The CRLH-TL with an additional λ/4-length TL is used as a harmonic tuner, which provides a short for even harmonics and an open for odd harmonics. PAs should provide highly efficient operation at a large BOP due to modulated signals with high PAPR. Therefore, Doherty PAs (DPAs) are the most attractable configuration to deliver high efficiency at a large BOP. In practice, DPA can？t deliver high efficiency at a large BOP and full output power due to soft turn-on effects of the transistors. In order to optimize the efficiency of DPA, various techniques such as uneven power drive, envelope tracking bias control, and high-efficiency SMPAs have been employed. However, they have been optimized at 6-dB BOP and are insufficient to provide high efficiency over 9-dB BOP. Also, the asymmetrical, N-way or multistage Doherty configurations can provide a wide efficiency range, but they result in low power gain and lay a burden on the drive amplifier due to N-way power splitter as well as complicated and less cost-effective design. In spite of the high-efficiency performance at a large BOP, DPAs show inherent poor linearity. Chapter 3 introduces various novel designs and applications of DPAs. In terms of efficiency optimization at a large BOP, asymmetrical DPA considering soft turn-on effects, unequal-cells-based DPA using uneven saturation power, and highly efficient DPA employing class-E topology are presented. For the linearity optimization, power-tracking DPAs using derivative superposition techniques and N-way DPAs with predistortion driver are shown. In the other word, the nonlinearity of the DPA is used as predistortion circuit for high-power amplifier linearization. In addition, a new distributed DPA is presented for wideband performance. For the linearity improvement of PAs, various linearization techniques have been widely researched and developed. Among various linearization techniques, feedfoward techniques provide excellent linearity improvement. But, they have not paid much attention to PA designers due to inherent efficiency-decreasing nature as well as bulky size and circuit complexity. Digital predistortion (DPD) approaches become a very promising method due to their high intermodulation (IM) suppression, but is complicated and implemented at the base band level. In other hand, analog predistortion (APD) techniques work at the RF with the advantage of simple circuitry and low cost. However, APDs haven't delivered the sufficient linearity improvement for modulated signals with wide signal bandwidth. One rea
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