Abstract ▼ AI-Helper

In this thesis, a fast locking integer-N PLL(Phase Locked-Loop) with dual Loop is proposed. The proposed PLL is consisted of two PFDs and CPs, two LPFs, a VCO, a divider and the LSI which is used for locking indicator. The proposed architecture operates at faster locking time than that of digital tu...

In this thesis, a fast locking integer-N PLL(Phase Locked-Loop) with dual Loop is proposed. The proposed PLL is consisted of two PFDs and CPs, two LPFs, a VCO, a divider and the LSI which is used for locking indicator. The proposed architecture operates at faster locking time than that of digital tuning PLL architectures. The proposed PLL has been designed based on a 0.18㎛ CMOS process with a 1.8V supply voltage, and simulated by HSPICE. Simulation result shows 110㎲ lock time at 900MHz output frequency.