Abstract ▼ AI-Helper

This thesis presents an interconnect reliability degradation monitoring circuitry to monitor the aging effects due to aggressive device scaling. The proposed interconnect reliability degradation monitoring circuitry is fabricated in a 0.13 μm CMOS technology. The circuit measures the effect of delay...

This thesis presents an interconnect reliability degradation monitoring circuitry to monitor the aging effects due to aggressive device scaling. The proposed interconnect reliability degradation monitoring circuitry is fabricated in a 0.13 μm CMOS technology. The circuit measures the effect of delay degradation on metal lines due to electromigration (EM) and time-dependent dielectric breakdown (TDDB). Two time amplifiers (TA) are used to detect small degradation effect on interconnect at an early stage. The TDC measures the amplified delay between the normal signal and the stressed signal with a resolution of 15ps. The ROM decoder is utilized to convert thermometer code generated by TDC into 4-bit binary code. The registers store the binary codes and keep them until the next measurement. As a result, the proposed monitoring circuit can sense tiny delay growth at the early degradation stage.

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