The advancement of electronic devices, the key factor of modern industrial development, is interlocked with the development of top-down process for physical miniaturization represented by Moor’s law. Accordingly, electronic devices have become ever smaller and faster. Silicon-based semiconductor...
The advancement of electronic devices, the key factor of modern industrial development, is interlocked with the development of top-down process for physical miniaturization represented by Moor’s law. Accordingly, electronic devices have become ever smaller and faster. Silicon-based semiconductor technology, however, has reached its physical limitation in terms of degree of integration and processing speed. To meet such demands, researchers demonstrate various materials such as graphene and developing new processes. Researches continue to release various next-generation electronic devices with graphene utilized in various processes. Many researchers also report their studies on applying graphene to the channel area within existing FET. Since graphene basically has a zero-band gap, when its electric properties are utilized, it can be a substitute materials of metallic materials such as transparent electrodes, but there needs to be a process to change the properties when its properties specifically for semiconductors is to be utilized. Based on theoretical analyses and experiments, some researches demonstrated the phenomenon of band gap opening, that is, the opening of a bandgap at normal temperature by reducing the width of graphene ribbons. However, top-down methods such as e-beam lithography that are utilized mainly for 10 nm or smaller graphene nano-ribbons are disadvantageous in that they require expensive facilities. It is also well known that in this type of processing step, the graphene may be damaged due to radiation from electron-beam. Hence, the necessity to develop other alternatives to prevent graphene from being damaged is emphasized in producing nano size patterns. In this report, we demonstrate a method of producing GNRs in large area by using electrospun PMMA nanofiber as a passivation mask and O2 plasma etching. This method is simple, inexpensive and fast to fabricate sub-micrometer width GNRs on a large scale while controlling their morphology and alignment. And by using this method we fabricated GNR-FETs with on/off ratio of 20.
The advancement of electronic devices, the key factor of modern industrial development, is interlocked with the development of top-down process for physical miniaturization represented by Moor’s law. Accordingly, electronic devices have become ever smaller and faster. Silicon-based semiconductor technology, however, has reached its physical limitation in terms of degree of integration and processing speed. To meet such demands, researchers demonstrate various materials such as graphene and developing new processes. Researches continue to release various next-generation electronic devices with graphene utilized in various processes. Many researchers also report their studies on applying graphene to the channel area within existing FET. Since graphene basically has a zero-band gap, when its electric properties are utilized, it can be a substitute materials of metallic materials such as transparent electrodes, but there needs to be a process to change the properties when its properties specifically for semiconductors is to be utilized. Based on theoretical analyses and experiments, some researches demonstrated the phenomenon of band gap opening, that is, the opening of a bandgap at normal temperature by reducing the width of graphene ribbons. However, top-down methods such as e-beam lithography that are utilized mainly for 10 nm or smaller graphene nano-ribbons are disadvantageous in that they require expensive facilities. It is also well known that in this type of processing step, the graphene may be damaged due to radiation from electron-beam. Hence, the necessity to develop other alternatives to prevent graphene from being damaged is emphasized in producing nano size patterns. In this report, we demonstrate a method of producing GNRs in large area by using electrospun PMMA nanofiber as a passivation mask and O2 plasma etching. This method is simple, inexpensive and fast to fabricate sub-micrometer width GNRs on a large scale while controlling their morphology and alignment. And by using this method we fabricated GNR-FETs with on/off ratio of 20.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.