Abstract ▼ AI-Helper

In the thesis, the doping process was studied using plasma immersion ion implantation (PIII) technique. As the scaling of complementary metal-oxide-semiconductor (CMOS) device approaches its physical limitations, PIII technique was applied to germanium (Ge) and graphene, the next-generation semicond...

In the thesis, the doping process was studied using plasma immersion ion implantation (PIII) technique. As the scaling of complementary metal-oxide-semiconductor (CMOS) device approaches its physical limitations, PIII technique was applied to germanium (Ge) and graphene, the next-generation semiconductor materials. Ge is a material that has high carrier mobility and low band gap compared to silicon (Si). Due to these properties, Ge can present potential applications for varying fields such as semiconductors, optical fibers, and solar cells. Graphene has high electron mobility, thermal conductivity, Young’s modulus, thin, and transparent properties. Graphene is applicable to solar cells, LEDs, mobile phones, and wearable devices.
In Chapter 3, PH3 PIII technique was used to implant phosphorus (P) into Ge epilayer grown on Si substrate. Silicon oxide (SiOx) layer was formed after ion implantation into Ge epilayer, followed by activation annealing process at the range of 500-800 °C in N2 atmosphere. The out-diffusion phenomenon of implanted P was investigated as a function of rapid thermal annealing (RTA) process temperature by comparing the presence or absence of the SiOx layer. PIII process caused damage to Ge epilayer as a form of a thin amorphous Ge layer. The thickness of the amorphous layer was calculated by simulation. Irrespective of SiOx capping layer, the sheet resistance decreased as the annealing temperature increased, which may be related to the recovery of ion implantation damages and the dopant activation. SiOx capping layer effectively suppressed the out-diffusion of P implanted into Ge epilayer and showed insignificant dopant loss during the annealing process. This resulted in lower sheet resistance of SiOx capped samples in the whole range than uncapped ones. Increasing the annealing process temperature reduced the number of defects induced by ion implantation and the number of misfit dislocations that occur during Ge epitaxial growth on Si. Moreover, the surface morphology of implanted Ge epilayer in the 800 °C annealing process was improved by softening and reflowing.
In Chapter 4, N2, PH3 PIII technique was used to implant nitrogen (N), P into graphene transferred on SiOx. Graphene transfer was performed using PMMA solution and Ohmic contact was confirmed using Au/Ti metal. PIII process caused damage to graphene surface, which suggests the possibility of chemical bonding increase with N, P, and hydrogen (H) ions. Multiple ion implantation increased the doping site, however, blocked the carrier transport path, leading to a decrease of current. The transferred graphene showed p-MOSFET characteristics due to ambient conditions such as oxidation. In N2-implanted graphene MOSFET, the bonding of graphitic-N is dominant among that of graphitic-N, pyridinic-N, and pyrrolic-N, which showed n-MOSFET. On the other hand, PH3-implanted graphene MOSFET showed that enhanced electrical properties of p-MOSFET by bonding H ions to graphene edge region due to damage induced by P ion implantation. However, in the as-implanted MOSFET, the on-off ratio was lowered by blocking the carrier transport path because of graphene surface damage by ion bombardment.

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