This paper proposes a divider structure that combines a carry-propagation-free division algorithm using RSD number system and a self-timed ring structure. The self-timed ring structure enables the divider to compute at a speed comparable to that of combinational array dividers with less silicon area. By exploiting the carry-propagation-free division algorithm, we can achieve further reduction of silicon area and computation time. The algorithm and structure of the proposed divider have been successfully verified through VHDL modeling and simulation. Preliminary experimental results show the effectiveness of the algorithm and structure.
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