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NTIS 바로가기電子工學會論文誌. Journal of the Institute of Electronics Engineers of Korea. SD, 반도체, v.41 no.10 = no.328, 2004년, pp.31 - 39
This paper illustrates the noise characteristics under chip's core operations according to types of packages and modules for DDR DRAM For analyzing this, the impedance profiles and power noises are analyzed with DRAM chips having commercial TSOP package and commercial FBGA package on TSOP-based DIMM...
J.-H. Choi, Y.-J. Kim, J.-K. Wee, and S. Lee, 'Pipelined Wake-Up Scheme to Reduce Power Line Noise for Block-Wise Shutdown of Low-Power VLSI Systems' IEICE trans. on Electronics, Vol. E87-C, No.4, pp629-633, April, 2004
A. Waizman and C.-Y. Chung, 'Resonant Free Power Network Design Using Extended Adaptive Voltage Positioning(EAVP) Methodology,' IEEE Transactions on Advanced Packaging, vol. 24, no. 3, pp. 236-245, Aug. 2001
M. Badaroglu, M. van Heijningen, V. Gravot, J. Compiet, S. Donnay, G. Gielen, and H. De Man, 'Modeling and Experimental Verification of Substrate Noise Generation in a 220-Kgates WLAN System-on-Chip with Multiple Supplies', IEEE Journal of Solid-State Circuits, vol. 38, no. 7, pp, 1250-1260, Jul. 2003
W. H. Ryo, H. Fahmy, and H. Maramis, 'High Frequency Simultaneous Switching Output Noise (SSO) Simulation Methodology For a DDR333/400 Data Interface,' Ansoft High-Speed Design Forum, July 2002
Y. Eo, W. R. Eisenstadt 'A Compact Multilayer IC Package Model for Efficient Simulation, Analysis, and Design of High-performance VLSI Circuits,' IEEE Transactions on Advanced Packaging, vol. 26, no. 4, pp. 392-401, Aug. 2003
S. M. Lee Y.-J. Kim, G. Moo, S. Lee, and J.-K. Wee, 'A Lumped-Circuit-Model-Based Design Method for Power Distribution Networks of Digital Circuit System', 7th IEEE Workshop on Signal Propagation on Interconnects' 2003, (Siena, Italy), pp.171-174. May 2003
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