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NTIS 바로가기電子工學會論文誌. Journal of the Institute of Electronics Engineers of Korea. SD, 반도체, v.43 no.7 = no.349, 2006년, pp.29 - 37
류순걸 (한양대학교 전자컴퓨터공학부) , 어영선 (한양대학교 전자컴퓨터공학부) , 심종인 (한양대학교 전자컴퓨터공학부)
This paper presents a new analytical model to suppress RLC resonance effects which inevitably occur in power/ground lines due to on-chip decoupling capacitor and other interconnect circuit parasitics (i.e., package inductance, on-chip decoupling capacitor, and output drivers, etc.). To characterize ...
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P. Heydari, and M. Pedram, 'Ground Bounce in' Digital VLSI Circuits,' IEEE Trans. VLSI Syst., vol. 11, pp. 180-193, April 2003
H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI. Addison-Wesley, 1990
C. Huang, Y,Yang and J.L.Prince, 'A simultaneous switching noise design algorithm for leadframe packages with or without ground plane.' IEEE T. on Components, Packaging, and Manufacturing Technology-Part B 19(1), pp. 15-22, Feb. 1996
A. J. Rainal, 'Eliminating inductive noise of external chip connections.' IEEE J. of SolidState Circuits 29(2), pp. 126-129, Feb. 1994
P. Larsson, 'di/dt noise in CMOS integrated circuits,' Analog Integrated Circuits and Signal Processing, no. 1/2, pp. 113-130, Sept. 1997
B. Young, Digital Signal Integrity. Prentice Hall, 2001
R. Senthinathan and J. L. Prince, 'Simultaneous switching ground noise calculation for packaged CMOS devices,' IEEE J. Solid-Sate Circuits, vol. 26, pp. 1724-1728, Nov. 1991
A. Vaidyanath, et al., 'Effect of CMOS driver ?loading conditions on simultaneous switching noise,' IEEE Trans. Comp., Packag., Manufact. Technol., vol. 17, pp. 480-485, Nov. 1994
S. R. Vemuru, 'Accurate simultaneous switching noise estimation including velocity-saturation effects,' IEEE Trans. Comp. Packag., Manufact. Technal. B, vol. 19, pp. 344-349, May 1996
Y. Eo, et al., 'New simultaneous switching noise analysis and modeling for high-speed and high-density CMOS IC package design,' IEEE Trans. Adv. Packag., vol. 23, pp. 303-312, May 2000
K Bathey et al., 'Noise computation in single chip packages,' IEEE Trans. Comp., Packag., Manufact. Technol. B, vol. 19, pp. 350-360, May 1996
T. Gabara, W. C. Fischer, J. Harrington, and W. W. Troutman, 'Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffer,' IEEE J. Solid State Circuits, vol. 32, pp. 407-418, Mar. 1997
P. Larsson, 'Resonance and damping in CMOS circuits with on-chip decoupling capacitance,' IEEE Trans. Circuits Syst., vol. 45, pp. 849-858, Aug. 1998
M. Ingels and M. Steyaert, 'Design strategies and decoupling techniques for reducing the effects of electrical interference in mixed-mode IC's,' IEEE J. Solid-State Circuits, vol. 32, pp. 1136-1141, July 1997
Artice M. Davis, Linear Circuit Analysis. PWS Publishing Company, 1998
X. Aragones, et al., Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs. Kluwer Academic Publishers, 1999
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