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NTIS 바로가기한국철도학회 논문집 = Journal of the Korean Society for Railway, v.10 no.1 = no.38, 2007년, pp.88 - 95
서민호 (인하대학교 대학원) , 박재현 (인하대학교 정보통신공학부) , 최영준 (삼성전자 DM 총괄연구소)
TCN(Train Communication Network) adopts the master/slave protocol to implement real-time communication. In this network, a fault on the master node, cased by either hardware or software failure, makes the entire communication impossible over TCN. To reduce fault detection and recovery time, this pap...
IEC 61375-1 Standard, Train Communication Network, 1999
UIC 556 Standard, Information Transportation on the Train Bus 1999.05.01 v2.0
H. Kirrmann and P.A. Zuber, 'IEC/IEEE Train Communication Network', 1996
Jimenez, J.;Martin, J.L.; Cuadrado, C.;Arias, J.;Lazaro,J.; 'A top-down design for the train communication network', Industrial Technology, 2003 IEEE International Conference on Volume 2, 10-12 Dec. 2003 Page(s) 1000-1005
Jimenez, J.;Martin, J.L.; Zuloaga, A.; Bidarte, U.;Arias,J; 'Comparison of two designs for the mutifunction vehicle bus' Computer -Aided Design of Integrated Circuits and System, IEEE Transactions on Volume 25, Issue 5, May 2006 Page(s):797-805
Moreno, J.C.; Laloya, E.J; Navarro,J; 'Line redundancy in MVB-TCN devices: a control unit design' Electrotechnical Conference, 2006. MELECON 2006. IEEE Mediterranean 16-19 May 2006 Page(s): 789-794
Bricaud, P.J., 'IP reuse creation for system-on-a-chip design', Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999 , 16-19 May 1999 Page(s): 395 -401
Benini, L.; De Micheli,G., 'Networks on chips: a new SoC paradigm', Computer, Volume: 35 Issue: 1 , Jan. 2002 ,Page: 70 -78
Lahiri, K.; Raghunathan, A.; Dey, S., 'Fast performance analysis of bus-based system-on-chip communication architectures', Comput er-Aided Design, 1999. Digest of Technical Papers. 1999 IEEE/ACM International Conference on , 7-11 Nov. 1999, Page(s): 566 -572
Lahtinen, V.; Kuusilinna, K.; Hamalainen, T., 'Optimizing finite state machines for system-on-chip communication', Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on , Volume: 1, 26-29 May 2002, Page(s): I-485-I-488 vol.1
Lahiri, K.; Raghunathan, A.; Lakshminarayana,G;.Dey,S,; Dey, S.; 'Design of high-performance system-on-chips using communicat ion architecture tuners' Computer-Aided Design of Integrated Circuits and systems, IEEE Transactions on Volume 23, Issue 5, May 2004 Page(s):620-636
Sunghyun Lee; Sungjoo Yoo; Kiyoung Choi, 'Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model', Hardware/Software Codesign, 2002. CODES 2002. Proceedings of the Tenth International Symposium on , 6-8 May 2002, Page(s): 199 -204
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