최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기電子工學會論文誌. Journal of the Institute of Electronics Engineers of Korea. SD, 반도체, v.45 no.9 = no.375, 2008년, pp.79 - 84
정상남 (한양대학교 전자전기제어계측공학과) , 백상현 (한양대학교 전자컴퓨터공학부)
Switching speeds increase in both frequency and the transition rate of edges. Inadequate forecast for simultaneous switching signals may cause designing the power planes without sufficient current capability. The delay of critical signals in a chip can be therefore inadvertently increased and the si...
* AI 자동 식별 결과로 적합하지 않은 문장이 있을 수 있으니, 이용에 유의하시기 바랍니다.
Payam Heydari, "Ground Bounce in Digital VLSI Circuits", IEEE Transaction on Very Large Scale Integration Systems, VOL. 11, NO. 2, April 2003
Yi-Shing Chang, Sandeep K. Gupta, "Analysis of Ground Bounce in Deep Sub-Micron Circuits", IEEE 15th VLSI Test Symposium, 1997
A. K. Stamper, J. E. Heidenreich, "Damascene Copper Integration", 4th International Symposium on Plasma Process-Induced Damage, 1999
Kenneth L. Shepard, Vinod Narayanan, "Noise in Deep Submicron Digital Design", IEEE/ACM InternationalComputer-Aided Design, November 1996
Howard H. Chen, "Minimizing Chip-Level Simultaneous Switching Noise for High- Performance Microprocessor Design", IEEE International Symposium on Circuit and Systems, VOL. 4, May 1996
Linda Milor, Larry Yu, Bill Liu, "Logic Product Speed Evaluation and Forecasting During The Early Phases of Process Technology Development Using Ring Oscillator Data", 2nd International Workshop on Statistical Metrology, 1997
E.Kreyszig,"Advanced Engineering Mathematics 8th edition", WILEY, pp. 848-850, 1999
※ AI-Helper는 부적절한 답변을 할 수 있습니다.