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NTIS 바로가기電子工學會論文誌. Journal of the Institute of Electronics Engineers of Korea. SD, 반도체, v.47 no.2=no.392, 2010년, pp.106 - 114
김정훈 (로스엔젤레스 캘리포니아 주립대학교 컴퓨터과학과)
We proposed an unified design methodology and verification platform for giga-scale System on Chip (SoC). According to the growth of VLSI integration, the existing RTL design methodology has a limitation of a production gap because a design complexity increases. A verification methodology need an evo...
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Daniel D. Gajski, Loganath Ramachandran, 'Introduction to High-Level Synthesis,' IEEE Design and Test of Computers, vol. 11, no. 4, pp. 44-54, Oct. 1994
P. Urard, A. Maalej, R. Guizzetti, N. Chawla, and V. Krishnaswamy, 'Leveraging sequential equivalence checking to enable system-level to RTL flows', Proceedings of Design Automation Conference, pp. 816 -821, San Francisco, CA, USA, Jun. 2008
Shireesh Verma, I.G Harris and Kiran Ramineni, 'Automatic Generation of Functional Coverage Models from Behavioral Verilog Descriptions,' Proceedings of Design, Automation & Test in Europe Conference & Exhibition, pp. 1-6 April 2007
P. Mishra and N. Dutt,, 'Functional coverage driven test generation for validation of pipelined processors,' Proceedings of Design, Automation and Test in Europe, pp. 678-683 Vol. 2 Jun. 2006
Unified Power Format (UPF) v1.0 Standard, http://www.unifiedpowerformat.com/
Janick Bergeron, Eduard Cerny, Alan Hunter, and Andy Nightingale, 'Verification Methodology Manual for SystemVerilog,' Springer, pp. 1-288, 2005
Kelvin Ng, 'Challenges in using system-level models for RTL verification,' Proceedings of Design Automation Conference, pp 812-815, San Francisco, CA, USA, Jun. 2008
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