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NTIS 바로가기Journal of the Institute of Electronics Engineers of Korea = 전자공학회논문지, v.50 no.10, 2013년, pp.76 - 81
하산 타릭 (조선대학교 정보통신공학과) , 최광석 (조선대학교 정보통신공학과)
A new phase frequency detector based digital phase-locked loop (PLL) of 125 MHz was designed using the 130 nm CMOS technology library consisting of inverting edge detectors along with a typical digital phase-locked loop to reduce the lock time and jitter for mid-frequency applications. XOR based inv...
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