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Accelerating Memory Access with Address Phase Skipping in LPDDR2-NVM 원문보기

Journal of semiconductor technology and science, v.14 no.6, 2014년, pp.741 - 749  

Park, Jaehyun (Department of Electrical Engineering and Computer Science, Seoul National University) ,  Shin, Donghwa (Department of Computer Engineering, Yeungnam University) ,  Chang, Naehyuck (Department of Electrical Engineering, Korea Advanced Institute of Science and Technology) ,  Lee, Hyung Gyu (School of Computer and Communication Engineering, Daegu University)

Abstract ▼ AI-Helper 아이콘AI-Helper

Low power double data rate 2 non-volatile memory (LPDDR2-NVM) has been deemed the standard interface to connect non-volatile memory devices such as phase-change memory (PCM) directly to the main memory bus. However, most of the previous literature does not consider or overlook this standard interfac...

주제어

#Phase-change memory   #LPDDR2-NVM   #main memory   #address phase skipping   #system-level implementation  

AI 본문요약
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제안 방법

  • 7% reduction with optimistic parameters of the PCM research prototype in industries. Finally, we verify the functionality of the proposed method by implementing a prototype that includes commercial PCM devices and our customized LPDDR2-NVM memory controller. For future work, we will evaluate the memory access time reduction of the proposed APS method with real applications in the prototype.
  • This paper introduces address phase skipping to accelerate memory access of non-volatile memory by utilizing existing resources as an extra level of cache. For practical comparison, we evaluate performance enhancement using various timing parameters, including commercial PCM devices that have far-from-optimistic parameters used in previous work. The extensive simulations demonstrate up to a 3.
  • Unlike traditional cache in the processor, we observe RDB hits for incoming memory accesses due to cache misses in the processor, because the effective size of RDB is bigger than the size of a single cacheline in the processor. In addition, the proposed method skips the part of the address phase when we observe RAB hits. This technique is only applicable for the LPDDR2-NVM main memory system.
  • We first explore the addressing architecture of the LPDDR2-NVM industry standard and propose address phase skipping (APS) by utilizing the existing resources, defined in the LPDDR2-NVM standard, as an extra level of cache [8]. The proposed technique covers the memory access patterns that are not exploited in cache memory. To verify the functionality and effectiveness of the proposed method, we develop a system-level prototype that equips an array of PCMs with an LPDDR2-NVM interface and a customized LPDDR2-NVM memory controller.
  • The proposed technique covers the memory access patterns that are not exploited in cache memory. To verify the functionality and effectiveness of the proposed method, we develop a system-level prototype that equips an array of PCMs with an LPDDR2-NVM interface and a customized LPDDR2-NVM memory controller. Simulation-based analysis with traces from real applications running on a full-system simulator supports the effectiveness of the proposed method, considering various design parameters that are not available in real industry prototypes.
  • We first verify the operation of the system-level prototype by using conventional memory test patterns, such as walking-0, walking-1, incremental address, inverse address, and fixed patterns.

대상 데이터

  • The prototype mainly consists of a control system-on-chip (SoC) and PCM small outline dual inline memory modules (SODIMMs), as shown in Fig. 5. The control SoC includes a MicroBlaze processor, our customized LPDDR2-NVM controller and many other conventional components.
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참고문헌 (17)

  1. "International Technology Roadmap for Semiconductors," 2012. 

  2. S. Raoux, et al., "Phase-change Random Access Memory: A Scalable Technology," IBM Journal of Research and Development, Vol. 52, No. 4/5, pp.1-11, 2010. 

  3. S. Cho and H. Lee, "Flip-N-Write: A Simple Deterministic Technique to Improve PRAM Write Performance, Energy and Endurance," in Proceedings of the 42nd Annual IEEE/ACM Inernational Symposium on Microachitecture, pp. 347-357, 2009. 

  4. M. K. Qureshi, V. Srinivasan, and J. A. Rivers, "Scalable High Performance Main Memory System Using Phase-Change Memory Technology," in Proceedings of the 36th Annual International Symposium on Computer Architecture, pp. 24-33, 2009. 

  5. B. C. Lee, et al., "Architecting Phase Change Memory as a Scalable DRAM Alternative," in Proceedings of the 36th Annual International Symposium on Computer Architecture, pp. 2-13, 2009. 

  6. H. Chung, et al., "A 58nm 1.8V 1Gb PRAM with 6.4MB/s Program BW," in Proceedings of the IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 500-502, 2011. 

  7. Y. Choi, et al., "A 20nm 1.8V 8Gb PRAM with 40MB/s Program Bandwidth," in Proceedings of the IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 46-48, 2012. 

  8. JEDEC, JESD209-F, 2013. 

  9. M. K. Qureshi, M. M. Franceschini, and L. A. Lastras-Montano, "Improving Read Performance of Phase Change Memories via Write Cancellation and Write Pausing," in Proceedings of the IEEE 16th International Symposium on High Performance Computer Architecture, pp. 1-11, 2010. 

  10. L. Jiang, et al., "Improving Write Operations in MLC Phase Change Memory," in Proceedings of the IEEE 18th International Symposium on High Performance Computer Architecture, pp. 1-10, 2012. 

  11. M. K. Qureshi, et al., "PreSET: Improving Performance of Phase Change Memories by Exploiting Asymmetry in Write Times," in Proceedings of the 39th Annual International Symposium on Computer Architecture, pp. 380-391, 2012. 

  12. X. Zhang, et al., "WoM-SET: Low Power Proactive-SET-based PCM Write using WoM Code," in Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design, pp. 217-222, 2013. 

  13. L. Jiang, et al., "FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multilevel Cell Phase Change Memory," in Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 1-12, 2012. 

  14. J. Yue and Y. Zhu, "Accelerating Write by Exploiting PCM Asymmetries," in Proceedings of the IEEE 19th International Symposium on High Performance Computer Architecture, pp. 282-293, 2013. 

  15. S. Rixner, et al., "Memory Access Scheduling," in Proceedings of the 27th annual international symposium on Computer architecture, pp. 128-138, 2000. 

  16. C. Bienia, et al., "The PARSEC Benchmark Suite: Characterization and Architectural Implications," in Proceedings of the 17th International Conference on Parallel Architectures and Compliation Techniques, pp. 72-81, 2008. 

  17. P. S. Magnusson, et al., "Simics: A full system simulation platform," Computer, Vol. 35, No. 2, pp. 50-58, 2002. 

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