[논문]A 120 GHz Voltage Controlled Oscillator Integrated with 1/128 Frequency Divider Chain in 65 nm CMOS Technology

Kim, Namhyung; Yun, Jongwon; Rieh, Jae-Sung

doi:10.5573/jsts.2014.14.1.131

[국내논문] A 120 GHz Voltage Controlled Oscillator Integrated with 1/128 Frequency Divider Chain in 65 nm CMOS Technology 원문보기

Journal of semiconductor technology and science, v.14 no.1, 2014년, pp.131 - 137

Kim, Namhyung (School of Electrical Engineering, Korea University) , Yun, Jongwon (School of Electrical Engineering, Korea University) , Rieh, Jae-Sung (School of Electrical Engineering, Korea University)

Abstract ▼ AI-Helper

A 120 GHz voltage controlled oscillator (VCO) with a divider chain including an injection locked frequency divider (ILFD) and six static frequency dividers is demonstrated using 65-nm CMOS technology. The VCO is designed based on the LC cross-coupled push-push structure and operates around 120 GHz. The 60 GHz ILFD at the first stage of the frequency divider chain is based on a similar topology as the core of the VCO to ensure the frequency alignment between the two circuit blocks. The static divider chain is composed of D-flip flops, providing a 64 division ratio. The entire circuit consumes a DC power of 68.5 mW with the chip size of $1385{\times}835{\mu}m^2$.

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제안 방법

In this work, we address this issue by proposing a D-band VCO integrated with a divider chain that employs an ILFD as the first stage of the chain based on 65-nm CMOS technology. The topology of the ILFD was taken similar to that of the VCO core thus making the locking less vulnerable to external uncertainties.
The area including probing pads is 1385 × 835 μm². The entire circuit, as well as the individual VCO and ILFD separated for testing, were measured through on-wafer probing using D-band and V-band measurement setups.
A 65-nm CMOS D-band push-push VCO integrated with a frequency divider chain of 1/128 division ratio composed of an ILFD stage 6 CML divider stages was demonstrated in this work. For accurate frequency alignment between the VCO and the ILFD, a similar topology was adopted for the two circuits with additional tuning capability for the ILFD.

대상 데이터

The circuit is composed of a 120 GHz push-push VCO, 60 GHz /2 ILFD, and a 6-stage static frequency divider as shown in Fig. 1. For the VCO, the second harmonic signal (2f₀) generated from the push-push operation can be taken as the output of PLL if completed, while the fundamental signal (f₀) is injected into the input node of the following ILFD.

이론/모형

The circuit was implemented using Samsung 65-nm CMOS technology. Fig.

참고문헌 (12)

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상세보기
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상세보기
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상세보기
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상세보기
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상세보기
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상세보기
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