[논문]A New Multi-site Test for System-on-Chip Using Multi-site Star Test Architecture

Han, Dongkwan; Lee, Yong; Kang, Sungho

doi:10.4218/etrij.14.0113.0469

A New Multi-site Test for System-on-Chip Using Multi-site Star Test Architecture 원문보기

ETRI journal, v.36 no.2, 2014년, pp.293 - 300

Han, Dongkwan (Department of Electrical and Electronics Engineering, Yonsei University) , Lee, Yong (Department of Electrical and Electronics Engineering, Yonsei University) , Kang, Sungho (Department of Electrical and Electronics Engineering, Yonsei University)

Abstract ▼ AI-Helper

As the system-on-chip (SoC) design becomes more complex, the test costs are increasing. One of the main obstacles of a test cost reduction is the limited number of test channels of the ATE while the number of pins in the design increases. To overcome this problem, a new test architecture using a channel sharing compliant with IEEE Standard 1149.1 and 1500 is proposed. It can significantly reduce the pin count for testing a SoC design. The test input data is transmitted using a test access mechanism composed of only input pins. A single test data output pin is used to measure the sink values. The experimental results show that the proposed architecture not only increases the number of sites to be tested simultaneously, but also reduces the test time. In addition, the yield loss owing to the proven contact problems can be reduced. Using the new architecture, it is possible to achieve a large test time and cost reduction for complex SoC designs with negligible design and test overheads.

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문제 정의

The main objective of this paper is the development of an on-chip DFT test architecture to maximize a multi-site test. The proposed multi-site star test architecture (MSTAR) can efficiently utilize the test channels of ATE without affecting other test channels, and allows a test analysis through the ATE channel without disrupting the multi-site test.

제안 방법

4 can support the testing and debugging process at the chip level. I-MSTARC selects at least one TAP controller from the embedded cores and the chip-level TAP controller to be tested, as E-MSTARC selects one DUT that is connected to the ATE to measure the test results. The test results of the selected core are evaluated through a daisy-chained TDI-TDO connection.
Goel [14] focused on the design and optimization of an on-chip test infrastructure, called a design for test (DFT) to facilitate high-throughput, multi-site wafer testing of large SoCs. The author also presented a test throughput model and considered parameters such as the test time, index time, abort-on-fail, and contact yield to increase the test throughput and reduce the test cost. This requires a controlling method for the interface between the cores and the ATE.
I-MSTARC selects at least one TAP controller from the embedded cores and the chip-level TAP controller to be tested, as E-MSTARC selects one DUT that is connected to the ATE to measure the test results. The test results of the selected core are evaluated through a daisy-chained TDI-TDO connection. I-MSTARC includes a shift register for the serial shift of data inputs with TMS or TDI in response to TCK and outputs the data in-parallel in response to nTRST.

대상 데이터

2. The proposed controller, which uses only IEEE Standard 1149.1-dedicated pins, is composed of star test architecture (STAR) registers in the form of shift registers controlled by input TAP pins. The test-logicreset state of IEEE Standard 1149.

이론/모형

1 and 1500 before being combined into an SoC chip. Once an SoC chip is integrated with several TAP cores, the test and debugging scheme should be compatible with IEEE standards of the chip level test, using the boundary scan register. IEEE standard 1149.
The external MSTARC (E-MSTARC) uses a chip ID code and an E-MSTAR register. We set the E-MSTAR register to the intended values using an IEEE Standard 1149.1-compliant method. The comparator always measures the value of the chip ID against the value of the E-MSTAR register.

성능/효과

The experimental results, using benchmark circuits show that MSTAR can test multiple DUTs and cores simultaneously, thus reducing the test time drastically. The results show that the test time reduction ratio over the previous works is very high with relatively small overhead.
91. The proposed method has the highest test time reduction ratio and the best throughput. The overhead comes from setting up the value of the MSTARC and measuring the test results of the embedded cores using MISR.
By adding a small circuitry to the DFT circuitry included in a complex SoC, the MSTR provides a direct path from the ATE to each SoC. The proposed method shows an outstanding performance in terms of test application time with a small area overhead.

참고문헌 (21)

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상세보기
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상세보기
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상세보기
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