본 연구에서는 Xilinx의 Zynq SoC (system on chip)를 이용하여 초음파 신호의 TOF (Time of Flight)를 측정한다. TOF는 특정 거리를 이동하는 데 소요되는 RF (radio frequency) 기준 신호와 초음파 신호의 시간차이로 부터 계산되고, 공기중 초음파의 속도를 곱하여 초음파 이동거리를 알아낸다. 이를 위해 Zynq의 내장 ADC, FIR (finite impulse response) 필터, Kalman 필터로부터 초음파 펄스를 생성하고, RF 인터페이스로부터 RF 기준펄스를 생성한다. Kalman 필터와 RF 인터페이스는 baremetal 멀티프로세싱에 의해 Zynq의 듀얼 프로세서 코어에 c-코드로 프로그래밍하고 나머지 구성 요소들은 Zynq의 FPGA 내에 설계하여, HW/SW co-design을 구현한다. 이를 통해 HW design에 비해 Zynq 자원의 가용률을 낮추고, 설계 시간을 대폭 줄일 수 있었다. 설계 툴로 Vivado IDE (integrated design environment)를 이용하여, 전체 신호처리 시스템을 계층적 블록 다이어그램의 형태로 설계하였다.
본 연구에서는 Xilinx의 Zynq SoC (system on chip)를 이용하여 초음파 신호의 TOF (Time of Flight)를 측정한다. TOF는 특정 거리를 이동하는 데 소요되는 RF (radio frequency) 기준 신호와 초음파 신호의 시간차이로 부터 계산되고, 공기중 초음파의 속도를 곱하여 초음파 이동거리를 알아낸다. 이를 위해 Zynq의 내장 ADC, FIR (finite impulse response) 필터, Kalman 필터로부터 초음파 펄스를 생성하고, RF 인터페이스로부터 RF 기준펄스를 생성한다. Kalman 필터와 RF 인터페이스는 baremetal 멀티프로세싱에 의해 Zynq의 듀얼 프로세서 코어에 c-코드로 프로그래밍하고 나머지 구성 요소들은 Zynq의 FPGA 내에 설계하여, HW/SW co-design을 구현한다. 이를 통해 HW design에 비해 Zynq 자원의 가용률을 낮추고, 설계 시간을 대폭 줄일 수 있었다. 설계 툴로 Vivado IDE (integrated design environment)를 이용하여, 전체 신호처리 시스템을 계층적 블록 다이어그램의 형태로 설계하였다.
In this research the TOF (time of flight) of ultrasonic signal is measured using Xilinx's Zynq SoC (system on chip). The TOF is calculated from the difference between periods during which RF (radio frequency) and ultrasonic signals come across a distance, and then travelling distance is obtained by ...
In this research the TOF (time of flight) of ultrasonic signal is measured using Xilinx's Zynq SoC (system on chip). The TOF is calculated from the difference between periods during which RF (radio frequency) and ultrasonic signals come across a distance, and then travelling distance is obtained by multiplying the TOF by the ultrasonic speed in the air. For this purpose, a ultrasonic pulse is generated from a Zynq's internal ADC, a FIR (finite impulse response) filter, and a Kalman filter. And a RF reference pulse is generated from a RF interface. Based on baremetal multiprocessing, the Kalman filter and the RF interface are c-programmed on Zynq's dual processor cores, with other components fabricated on Zynq's FPGA. With this HW/SW co-design, both lower resource utilization and much smaller designing period were obtained than the HW design. As a design tool, Vivado IDE(integrated design environment) is used to design the whole signal processing system in hierarchical block diagrams.
In this research the TOF (time of flight) of ultrasonic signal is measured using Xilinx's Zynq SoC (system on chip). The TOF is calculated from the difference between periods during which RF (radio frequency) and ultrasonic signals come across a distance, and then travelling distance is obtained by multiplying the TOF by the ultrasonic speed in the air. For this purpose, a ultrasonic pulse is generated from a Zynq's internal ADC, a FIR (finite impulse response) filter, and a Kalman filter. And a RF reference pulse is generated from a RF interface. Based on baremetal multiprocessing, the Kalman filter and the RF interface are c-programmed on Zynq's dual processor cores, with other components fabricated on Zynq's FPGA. With this HW/SW co-design, both lower resource utilization and much smaller designing period were obtained than the HW design. As a design tool, Vivado IDE(integrated design environment) is used to design the whole signal processing system in hierarchical block diagrams.
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제안 방법
Accepting the output from the ABSfnc block via axigpio module, Zynq’s dual-core processor block (ZYNQ_PS7) performs the Kalman filtering, ultrasound and RF pulse generations, and TOF and moving distance calculations.
In this study, an ultrasonic TOF measuring system using the Zynq SoC-based baremetal multiprocess is proposed and its test results are shown. The system is designed with Vivado and implemented by using only a Zynq SoC.
The whole system was designed by using the baremetal multiprocessing with three parts, ultrasonic pulse generation, RF pulse generation, and TOF calculation. With suitable IPs (Intellectual property)[2], components are fabricated on the FPGA by the IPs, or, components are programed on processor cores by the c-programs.
대상 데이터
1 shows entire system block diagram. The ultrasonic transmitter consists of a ultrasonic sender module and a RF module, and the ultrasonic receiver consists of a ultrasonic sensor, a RF module, and a Zynq-7010 board[11]. The transmitter transmits 40kHz ultrasonic signal and 2.
이론/모형
The entire system is designed by the Xilinx’s Vivado IDE (Integrated Design Environment)[10] in the form of hierarchical block diagrams.
성능/효과
7. According to the utilization results, it can be seen that not only DSP slice (DSP48) utilization of the HW design becomes double compared to the HW/ SW co-design but considering other resources, HW/ SW co-design is more efficient than the HW design in resource utilization.
후속연구
From the figure, it can be seen that the distances varies within about 3 cm depending on the reference levels and increases as the level increases. Future research will be conducted to obtain more accurate measurement results by compensating the variance according to the comparison level and by designing digital filters.
참고문헌 (14)
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P. Wehner, M. Ferger, D. Gohringer and M. Hubner, "Rapid prototyping of a portable HW/SW co-design on the virtual zynq platform using SystemC," IEEE 26th International Conference on SOC(SOCC), pp. 296-300, 2013.
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A. Schmidt, "Profiling bare-metal cores in AMP systems," System, Software, SoC and Silicon Debug Conference, pp. 1-4, 2012.
J. McDougall, "Simple AMP: bare-metal system running on both Cortex-A9 processors," Application Note: Zynq-7000 AP SoC, Xilinx, Jan. 24, 2014.
J. C. Jackson, R. Summan, S. M. Whiteley, S. G. Pierce, and G. Hayward, "Time-of-flight measurement techniques for airborne ultrasonic ranging," IEEE Trans. Ultrason. Ferroelectr. Freq. Control, Vol. 60, no. 2, pp. 343-355, 2013.
Vivado design suite user guide, programming and debugging, Xilinx, Apr. 2014.
ZYBO reference manual, digilent, Feb. 2014.
B. G. Lim and M. H. Kang, "HW/SW co-design for an ultrasonic signal processing system using Zynq SoC," Journal of The Institute of Electronics Engineers of Korea, Vol. 51, no. 8, pp. 148-155, August 2014.
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