[논문]고정 샘플링 주파수에서의 모듈형 멀티레벨 컨버터 레벨 선택 알고리즘

김찬기; 박창환; 김장목

doi:10.6113/tkpe.2018.23.6.415

[국내논문] 고정 샘플링 주파수에서의 모듈형 멀티레벨 컨버터 레벨 선택 알고리즘
Level Selection Algorithm with Fixed Sampling Frequency for Modular Multilevel Converter 원문보기

전력전자학회 논문지 = The Transactions of the Korean Institute of Power Electronics, v.23 no.6, 2018년, pp.415 - 423

김찬기 (Power Transmission Laboratory, KEPCO Research Institut) , 박창환 (Dept. of Electrical Eng., Pusan National University) , 김장목 (Dept. of Electrical Eng., Pusan National University)

Abstract ▼ AI-Helper

This study uses a level selection algorithm with fixed sampling frequency for modular multilevel converter (MMC) systems. Theoretically, the proposed method increases the level infinitely while the sampling time remains the same. The proposed method called cluster stream buffer (CSB) consists of several clusters, wherein each cluster is composed of 32 submodules that depend on the level of the submodules in the MMC system. To increase the level of the MMC system, additional clusters are used, and the sampling time between clusters is determined from the sampling time between levels needed for utilizing the entire level from the MMC system. This method is crucial in the control of MMC-type HVDC systems because it improves scalability and precision.

Keyword

표/그림 (16)

그림 Fig. 1. Basic structure of MMC.
그림 Fig. 2. ABB’S Group Module based MMC.
그림 Fig. 3. Pole voltage of ABB’s MMC using group module topology.
그림 Fig. 4. Single-phase equivalent circuit of MMC.
그림 Fig. 5. MMC Control Diagram with NLC Modulation.
그림 Fig. 6. Output voltage of NLC with small sampling interval.
그림 Fig. 8. Actual implementation of the proposed “Cluster stream buffer” method for MMC.
그림 Fig. 7. Output voltage of NLC with large sampling interval.
그림 Fig. 9. Cluster module based MMC arm.
그림 Fig. 10. Cluster module based MMC controller H/W structure.
그림 Fig. 11. Output voltage level of MMC based VSC-HVDC without cluster stream buffer method.
그림 Fig. 12. Output voltage level of MMC based VSC-HVDC using cluster stream buffer method.
그림 Fig. 13. Simulation result of the proposed algorithm: Cluster stream buffer.
그림 Fig. 14. Simulation result of conventional method. (a) Upper and lower arm voltages, (b) Three phase output current.
그림 Fig. 15. Simulation result of proposed method. (a) Upper and lower arm voltages, (b) Three phase output current.
표 TABLE I SIMULATION PARAMETER OF GRID CONNECTEDMMC SYSTEM

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가설 설정

- The output voltage is smooth and nearly ideal sinusoidal, which means only small or even no filters are required.

제안 방법

Finally, a time-domain simulation model with 325 SMs per arm is implemented in MATLAB/Simulink to validate the performance of the proposed NLC modulation scheme using the “Cluster Stream Buffer” in MMC system.
Relatively, the NLC modulation is easier to be implemented for HVDC system. Due to the conceptual implementation simplicity of the NLC method, the aim is to use it in converters with a high number of levels^[9] . If the HVDC system has a sufficiently large number of submodules, a relatively low harmonic amplitude and THD could be achieved by using NLC modulation.
9, the proposed cluster stream buffer method arranges the MMC system as a combinations of clusters, where each cluster is composed of 32 submodules, and the number of the cluster increases as the submodule level (or voltage level) increases. The advantages of the proposed method is to ensure the scalability of the MMC system while keeping the sampling time constant, and improve the precision of the control system in the MMC HVDC system.
Unlike the group module approach used by ABB, which switches the series connection of the IGBT devices simultaneously, the proposed algorithm switches the cluster connection of the IGBT devices one by one. The individual switching of the IGBTs reduce the harmonic content of the converter system which have a significant effect specially in the high level MMC system.
However, selecting 16 IGBTs in a cluster needs many cluster controllers while expanding the MMC system to a higher level and selecting 64 IGBTs in a cluster causes a reduction in the reliability and the control resolution of the system. Therefore, in order to optimize both the number of controller and reliability of the system, this paper organizes each cluster to have 32 IGBTS. Then, the output voltage of the MMC based VSC-HVDC system using the proposed method has a much higher level as shown in Fig.
In this paper, a new switching topology for easily expanding the MMC capacity to several levels while maintaining fixed sampling time is presented and validated. An explanation to the difference in the harmonics of the converter output voltages during group module and cluster approach was given.

대상 데이터

The simulation of the cluster stream buffer method is implemented using MATLAB/Simulink platform. The model used in the simulation is composed of 11 cluster and each of the cluster has 32 submodules, which results a total of 352 submodules in one arm of the MMC system. Fig.

이론/모형

This paper deals with the NLC implementation method of the “Cluster Stream Buffer” which uses grouping and controlling the submodules, based on the time division method.
12. Output voltage level of MMC based VSC-HVDC using cluster stream buffer method.
The simulation of the cluster stream buffer method is implemented using MATLAB/Simulink platform. The model used in the simulation is composed of 11 cluster and each of the cluster has 32 submodules, which results a total of 352 submodules in one arm of the MMC system.

참고문헌 (14)

R. Marquardt, "Stromrichterschaltungen mit verteilten energiespeichern," German Patent DE 10103031A1, Jan. 24, 2001.
A. Lesnicar and R. Marquardt, "An innovative modular multilevel converter topology suitable for a wide power range," in Proc. IEEE Power Tech Conf., Bologna, Italy, pp. 6, 2003.
A. Lesnicar and R. Marquardt, "A new modular voltage source inverter topology," presented at the EPE, Toulouse, France, Sep. 2003.
J. Dorn, H. Huang, and D. Retzmann, "A new multilevel voltage sourced converter topology for HVDC applications," in CIGRE Session, Paris, France, 2008.
G. S. Konstantinou and V. G. Agelidis, "Performance evaluation of half-bridge cascaded multilevel converters operated with multicarrier sinusoidal PWM techniques," in Proc. IEEE Industrial Electronics and Applications Conf., pp. 3399-3404, 2009.
D. Zhong, L. M. Tolbert, J. N. Chiasson, and B. Ozpineci, "Reduced switching-frequency active harmonic elimination for multilevel converters," IEEE Trans. Ind. Electron., Vol. 55, No. 4, pp. 1761-1770, Apr. 2008.

상세보기
D. Zhong, L. M. Tolbert, and J. N. Chiasson, "Active harmonic elimination for multilevel converters," IEEE Trans. Power Electron., Vol. 21, No. 2, pp. 459-469, Mar. 2006.

상세보기
B. Ozpineci, L. M. Tolbert, and J. N. Chiasson, "Harmonic optimization of multilevel converters using genetic algorithms," IEEE Power Electron. Lett., Vol. 3, No. 3, pp. 92-95, Sep. 2005.
S. Sirisukprasert, L. J. Sheng, and L. T. Hua, "Optimum harmonic reduction with a wide range of modulation indexes for multilevel converters," IEEE Trans. Ind. Electron., Vol. 49, No. 4, pp. 875-881, Aug. 2002.

상세보기
M. Glinka and R. Marquardt, "A new AC/AC multilevel converter family," IEEE Trans. Ind. Electron., Vol. 52, No. 3, pp. 662-669, Jun. 2005.

상세보기
L. Pu, W. Yue, and C. Wulong, "Grouping-sorting optimized model predictive control of modular multilevel converter with reduced computational load," in 9th International Conference on Power Electronics and ECCE Asia (ICPE-ECCE Asia), Jul. 2015.
B. Xia, Y. Li, and Z. Li, "A distributed voltage balancing method for modular multilevel converter," in IEEE 3rd International Future Energy Electronics Conference and ECCE Asia (IFEEC 2017-ECCE Asia), Jul. 2017.
Q. Tu and Z. Xu, "Impact of sampling frequency on harmonic distortion for modular multilevel converter," IEEE Trans. on Power Delivery, Vol. 26, No. 1, pp. 298-306, Dec. 2010.
H. R. Campos and F. M. David, "Selective harmonic elimination for the modular multilevel converter," North American Power Symposium (NAPS), Sep. 2016.

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DOI : 10.6113/TKPE.2018.23.6.415 [무료]
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