[논문]Design and FPGA Implementation of FBMC Transmitter by using Clock Gating Technique based QAM, Inverse FFT and Filter Bank for Low Power and High Speed Applications

Sivakumar, M.; Omkumar, S.

doi:10.5370/jeet.2018.13.6.2479

Design and FPGA Implementation of FBMC Transmitter by using Clock Gating Technique based QAM, Inverse FFT and Filter Bank for Low Power and High Speed Applications 원문보기

Journal of electrical engineering & technology, v.13 no.6, 2018년, pp.2479 - 2484

Sivakumar, M. (Dept. of Electronics and Communication Engineering, SCSVMV) , Omkumar, S. (Dept. of Electronics and Communication Engineering, SCSVMV)

Abstract ▼ AI-Helper

The filter bank multicarrier modulation (FBMC) technique is one of multicarrier modulation technique (MCM), which is mainly used to improve channel capacity of cognitive radio (CR) network and frequency spectrum access technique. The existing FBMC System contains serial to parallel converter, normal QAM modulation, Radix2 inverse FFT, parallel to serial converter and poly phase filter. It needs high area, delay and power consumption. To further reduce the area, delay and power of FBMC structure, a new clock gating technique is applied in the QAM modulation, radix2 multipath delay commutator (R2MDC) based inverse FFT and unified addition and subtraction (UAS) based FIR filter with parallel asynchronous self time adder (PASTA). The clock gating technique is mainly used to reduce the unwanted clock switching activity. The clock gating is nothing but clock signal of flip-flops is controlled by gate (i.e.) AND gate. Hence speed is high and power consumption is low. The comparison between existing QAM and proposed QAM with clock gating technique is carried out to analyze the results. Conversely, the proposed inverse R2MDC FFT with clock gating technique is compared with the existing radix2 inverse FFT. Also the comparison between existing poly phase filter and proposed UAS based FIR filter with PASTA adder is carried out to analyze the performance, area and power consumption individually. The proposed FBMC with clock gating technique offers low power and high speed than the existing FBMC structures.

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제안 방법

In this paper, low area, low power and high speed filter bank multi carrier (FBMC) transmitter with clock gating technique is proposed by using modified R2MDC based IFFT, modified QAM modulation and UAS based FIR filter with clock gating technique. Simulation is carried out to check the functionality of FBMC transmitter.
In this paper, the design of existing and proposed QAM modulation, Existing and proposed IFFT, existing and proposed filter are designed using Verilog HDL language. These three modifications are included in FBMC transmitter structure.

성능/효과

The first the comparison between existing radix2 IFFT and pipelined based R2MDC is carried out. From the obtained results it shows that the pipelined based R2MDC IFFT offers 38.55% area reduction and 1% power reduction than the existing radix2 IFFT. But the delay is increased and speed is decreased.
Further to improve the speed and decrease the delay, the clock gating based UAS filter with PASTA adder is designed. From the results, it denotes that the proposed clock gating based UAS filter with PASTA adder offers 79.26% area reduction, 40.09% power reduction and 60.21% delay reduction than the existing poly phase filter. Finally, these three modifications are included in FBMC transmitter structure.
Initially, the comparison between existing and proposed QAM modulation is performed to analyze area, delay and power as shown in Table 1. From the results, it shows that the proposed QAM modulation with clock gating techniques offers 1% area reduction, 1% power reduction and 40% delay reduction than the existing QAM modulation.
38% delay reduction than the existing FBMC transmitter. Similarly, the proposed FBMC with clock gating technique offers 4.32% area reduction, 32.97% power reduction and 88.03% delay reduction than the existing FBMC transmitter.
Comparison between existing and proposed FBMC is performed and the results are given in Table 4. The proposed FBMC without clock gating technique is compared with the existing FBMC transmitter and results says that the proposed FBMC without clock gating gives 5.75% area reduction, 21.86% power reduction and 72.38% delay reduction than the existing FBMC transmitter. Similarly, the proposed FBMC with clock gating technique offers 4.
But the delay is very high. To overcome this problem, the proposed UAS filter with PASTA adder is used, which gives 80.64% area reduction, 27.43% power reduction and 47.23% delay reduction than the existing poly phase filter. Further to improve the speed and decrease the delay, the clock gating based UAS filter with PASTA adder is designed.

참고문헌 (20)

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상세보기
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Design and FPGA Implementation of FBMC Transmitter by using Clock Gating Technique based QAM, Inverse FFT and Filter Bank for Low Power and High Speed Applications 원문보기

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Design and FPGA Implementation of FBMC Transmitter by using Clock Gating Technique based QAM, Inverse FFT and Filter Bank for Low Power and High Speed Applications 원문보기

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