[논문]빠른 상승 시간을 갖는 파워 셀 기반 펄스 파워 모듈레이터

이승희; 송승호; 류홍제

doi:10.6113/tkpe.2021.26.1.25

빠른 상승 시간을 갖는 파워 셀 기반 펄스 파워 모듈레이터
Power Cell-based Pulsed Power Modulator with Fast Rise Times 원문보기

전력전자학회 논문지 = The Transactions of the Korean Institute of Power Electronics, v.26 no.1, 2021년, pp.25 - 31

이승희 (Department of Energy System Engineering, Chung-Ang University) , 송승호 (Department of Energy System Engineering, Chung-Ang University) , 류홍제 (Department of Energy System Engineering, Chung-Ang University)

Abstract ▼ AI-Helper

This paper describes the design of a power cell-based pulsed power modulator with fast rise times. The pulse-generating section of the pulse power modulator is a series stack of power cells. Each power cell is composed of a storage capacitor, a pulse switch, and a bypass diode. When the pulse switches are turned on, the capacitors are connected in series and the sum of voltages is applied to the load. For output pulses with fast rise times, an IGBT with fast turn-on characteristics is adopted as a pulse switch and the optimized gate driving method is used. Pspice simulation is performed to account for the gate driving method. A 10 kV, 12-power cell-based pulsed power modulator is tested under resistive load and plasma reactor load. The rise times of output pulses less than 20 ns are confirmed, showing that the pulsed power modulator can be effectively applied to pulsed power applications with fast rise times.

주제어

표/그림 (11)

그림 Fig. 1. Schematic of the fast rise time pulsed power modulator based on power cell.
그림 Fig. 2. Operational modes of power cell stack. (a) Normal operation mode, (b) Malfunctioning operation mode.
그림 Fig. 3. The results of the single cell tests for rise time comparison.
그림 Fig. 4. Gate control scheme for pulse switches.
그림 Fig. 5. Operational modes of inverter switch (S1). (a) Delay mode, (b) Gate charging mode, (c) Gate discharging mode.
그림 Fig. 6. Simulation results of gate driving scheme for narrow gate voltage.
그림 Fig. 7. Operational modes of inverter switch (S2/S4). (a) Bypass mode, (b) Gate charging mode.
그림 Fig. 8. Simulation results of gate driving scheme for fast-rising gate voltage.
그림 Fig. 9. Experimental waveforms of the control-loop gate control scheme.
그림 Fig. 10. Experimental waveform of 10 kV/45 A output pulse.
그림 Fig. 11. Pulse discharge test under plasma reactor. (a) Experimental waveforms of output pulse voltage under plasma reactor load, (b) Corona discharge inside the reactor.

참고문헌 (12)

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