[논문]차동 노이즈 분석을 위한 단상 인버터 고주파 회로 모델링 및 검증

신주현; 생차야; 김우중; 차한주

doi:10.6113/tkpe.2021.26.3.176

차동 노이즈 분석을 위한 단상 인버터 고주파 회로 모델링 및 검증
Single Phase Inverter High Frequency Circuit Modeling and Verification for Differential Mode Noise Analysis 원문보기

전력전자학회 논문지 = The Transactions of the Korean Institute of Power Electronics, v.26 no.3, 2021년, pp.176 - 182

신주현 (Dept. of Electrical Engineering, Chungnam National University) , 생차야 (Dept. of Electrical Engineering, Chungnam National University) , 김우중 (Battery Management System Team, SK Innovation) , 차한주 (Dept. of Electrical Engineering, Chungnam National University)

Abstract ▼ AI-Helper

This research proposes a high-frequency circuit that can accurately predict the differential mode noise of single-phase inverters at the circuit design stage. Proposed single-phase inverter high frequency circuit in the work is a form in which harmonic impedance components are added to the basic single-phase inverter circuit configuration. For accurate noise prediction, parasitic components present in each part of the differential noise path were extracted. Impedance was extracted using a network analyzer and Q3D in the measurement range of 150 kHz to 30 MHz. A high-frequency circuit model was completed by applying the measured values. Simulations and experiments were conducted to confirm the validity of the high-frequency circuit. As a result, we were able to predict the resonance point of the differential mode voltage extracted as an experimental value with a high-frequency circuit model within an approximately 10% error. Through this outcome, we could verify that differential mode noise can be accurately predicted using the proposed model of the high-frequency circuit without a separate test bench for noise measurement.

주제어

표/그림 (27)

그림 Fig. 1. Grid-connected single phase inverter circuit.
그림 Fig. 2. DC link current of single-phase inverter.
그림 Fig. 3. Differential mode path impedance.
그림 Fig. 4. Impedance measurement internal circuit diagram of GP series method.
그림 Fig. 5. Capacitor parasitic impedance measurement using GP series method.
그림 Fig. 6. Results of capacitor parasitic impedance with GP series method
그림 Fig. 7. IGBT impedance measurement using GP series method.
그림 Fig. 8. Results of IGBT parasitic impedance measurements using the GP series method.
그림 Fig. 9. PCB track parasitic impedance measurement section.
표 TABLE I MEASUREMENT SPEC
표 TABLE Ⅱ E5061B EQUIVALENT CIRCUIT D MODEL
그림 Fig. 10. (a) PCB pattern extraction, (b) Electrical signal injection into the pattern to be analyzed.
그림 Fig. 11. Measured using Q3D L_{PCB_P1}.
그림 Fig. 12. Configuration of DC bus plates.
그림 Fig. 13. 3D modeled DC bus plate.
그림 Fig. 14. Impedance extraction of DC bus plates using electrical signals.
그림 Fig. 15. Measured using Q3D L_DC+.
그림 Fig. 16. single phase inverter high frequency model.
그림 Fig. 17. Psim circuit to measure differential mode voltage of single phase inverter.
표 TABLE Ⅲ IMPEDANCE PARAMETER MEASUREMENT RESULT
표 TABLE Ⅳ SIMULATION PARAMETER
그림 Fig. 18. Differential-model noise voltage simulation results.
그림 Fig. 19. CISPR 25 LISN.
그림 Fig. 20. Test bench to measure differential mode voltage of single phase inverter.
그림 Fig. 21. Used power splitter.
그림 Fig. 22. Differential-model noise voltage comparison results. (a) Experimental, (b) Simulation.
표 TABLE Ⅴ TEST EQUIPMENT

참고문헌 (10)

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상세보기
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