[논문]Simulation-Based Fault Analysis for Resilient System-On-Chip Design

Han, Chang Yeop; Jeong, Yeong Seob; Lee, Seung Eun

doi:10.6109/jicce.2021.19.3.175

Simulation-Based Fault Analysis for Resilient System-On-Chip Design 원문보기

Journal of information and communication convergence engineering, v.19 no.3, 2021년, pp.175 - 179

Han, Chang Yeop (Department of Electronic Engineering, Seoul National University of Science and Technology) , Jeong, Yeong Seob (Department of Electronic Engineering, Seoul National University of Science and Technology) , Lee, Seung Eun (Department of Electronic Engineering, Seoul National University of Science and Technology)

Abstract ▼ AI-Helper

Enhancing the reliability of the system is important for recent system-on-chip (SoC) designs. This importance has led to studies on fault diagnosis and tolerance. Fault-injection (FI) techniques are widely used to measure the fault-tolerance capabilities of resilient systems. FI techniques suffer from limitations in relation to environmental conditions and system features. Moreover, a hardware-based FI can cause permanent damage to the target system, because the actual circuit cannot be restored. Accordingly, we propose a simulation-based FI framework based on the Verilog Procedural Interface for measuring the failure rates of SoCs caused by soft errors. We execute five benchmark programs using an ARM Cortex M0 processor and inject soft errors using the proposed framework. The experiment has a 95% confidence level with a ±2.53% error, and confirms the reliability and feasibility of using proposed framework for fault analysis in SoCs.

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표/그림 (5)

그림 Fig. 1. Overview of the System-on-Chip Fault Analyzer (SoCFA) framework: (a) block diagram of the SoCFA. (b) Verilog Procedural Interface (VPI) function call in the testbench, and (c) gate-level netlist under diagnosis.
그림 Fig. 2. System flow of the SoCFA for fault diagnosis.
표 Table 1. Description of the System-on-Chip Fault Analyzer (SoCFA) functions
그림 Fig. 3. Failure rates of the Cortex M0 processor with different workloads under a 10⁻⁸ soft error.
표 Table 2. Information of benchmarks running on an ARM Cortex M0 processor

참고문헌 (13)

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Simulation-Based Fault Analysis for Resilient System-On-Chip Design 원문보기

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