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NTIS 바로가기전기전자학회논문지 = Journal of IKEEE, v.26 no.4, 2022년, pp.659 - 670
이종혁 (Dept. of Electronics Engineering, Graduate School, Kumoh National Institute of Technology) , 송창민 (Dept. of Electronics Engineering, Graduate School, Kumoh National Institute of Technology) , 장영찬 (Dept. of Electronics Engineering, Graduate School, Kumoh National Institute of Technology)
An 830-Mb/s/pin transceiver for a controller supporting ×32 LPDDR2 memory is designed. The transmitter consists of eight unit circuits has an impedance in the range of 34Ω ∽ 240Ω, and its impedance is controlled by an impedance correction circuit. The transmitted DQS sign...
Jessie Shen, "Samsung develops wide I/O mobile DRAM for smartphones, tablets," https://www.digitimes.com/news/a20110222PR200.html
JEDEC, "LOW POWER DOUBLE DATA RATE 2 (LPDDR2)," https://www.jedec.org/
M. Bazes, "Two novel fully complementary?self-biased CMOS differential amplifiers," IEEE?Journal of Solid-State Circuits, vol.26, no.2,?pp.165-168, 1991. DOI: .1109/4.68134
Churoo Park et al., "A 512-mb DDR3 SDRAM?prototype with C/sub IO/ minimization and self-calibration techniques," IEEE Journal of Solid-State Circuits, vol.41, no.4, pp.831-838, 2006.?DOI: 10.1109/JSSC.2006.870808
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