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NTIS 바로가기반도체공학회 논문지 = Transactions on semiconductor engineering, v.2 no.1, 2024년, pp.1 - 8
윤종호 (Department of Electrical Engineering, Pohang University of Science and Technology) , 이승규 (Hyosung Ventures) , 강석형 (Department of Electrical Engineering, Pohang University of Science and Technology)
When processing depthwise separable convolution, low utilization of processing elements (PEs) is one of the challenges of systolic array (SA). In this study, we propose a new SA architecture to maximize throughput in depthwise convolution. Moreover, the proposed SA performs subsequent pointwise conv...
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