최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기Computer, v.26 no.11, 1993년, pp.20 - 31
Johnson, K.T. (Pennsylvania State Univ., University Park, PA, USA) , Hurson, A.R. (Pennsylvania State Univ., University Park, PA, USA) , Shirazi, B.
The extension of systolic array architecture from fixed- or special-purpose architectures to general-purpose, SIMD (single-instruction stream, multiple-data stream), MIMD (multiple-instruction stream, multiple-data stream) architectures, and hybrid architectures that combine both commercial and FPGA...
Proc Int'l Conf Parallel Processing Block Processing on a Programmable Systolic Array friedlander 1987 184
Proc IEEE Computers and Digital Technology Systolic Realization for 2D Convolution Using Configurable Functional Method in VLSI Parallel Array Designs wenyang 1991 10.1049/ip-e.1991.0050 138 361
Fortes, Wah. Guest Editors' Introduction: Systolic Arrays-From Concept to Implementation. Computer, vol.20, no.7, 12-17.
Systolic Array Processors jones 1989 459
Schröder, H., Strazdins, P.. Program compression on the instruction systolic array. Parallel computing, vol.17, no.2, 207-219.
Proc Int'l Conf Parallel Processing B-SYS: A 470-Processor Programmable Systolic Array hughcy 1991 1580
Systolic Array Processors krikelis 1989 287
Smith, R., Sobelman, G.. Simulation-based design of programmable systolic arrays. Computer aided design, vol.23, no.10, 669-675.
Computer Wafer-Scale Integration: Architectures and Algorithms fuchs 1992 25 6
Proc Int'l Conf Parallel Processing Splash: A Reconfigurable Linear Logic Array gokhalc 1990 1526
Proc Soc of Photo-Optical Instrumentation Engineers Real-lime Signal Processing VII Experience with the CMU Programmable Systolic Chip fisher 1984 495
Smith, R., Sobelman, G.. Simulation-based design of programmable systolic arrays. Computer aided design, vol.23, no.10, 669-675.
Gokhale, M., Holmes, W., Kopser, A., Lucas, S., Minnich, R., Sweely, D., Lopresti, D.. Building and using a highly parallel programmable logic array. Computer, vol.24, no.1, 81-89.
Foulser, D.E., Schreiber, R.. The Saxpy Matrix-1: A General-Purpose Systolic Computer. Computer, vol.20, no.7, 35-43.
Progeammation des Mega-Processeurs du GAPP � la Connection Machine Course Notes DEA Artificial Intelligence oreussay 1985
Malek, M., Opper, E.. The cylindrical banyan multicomputer: A reconfigurable systolic architecture. Parallel computing, vol.10, no.3, 319-327.
Systolic Array Processors jones 1989 459
Snyder. Introduction to the configurable, highly parallel computer. Computer, vol.15, no.1, 47-56.
Proc Eighth Int'l Conf Pattern Recognition PICAP3: A Parallel Processor Tuned for 3D Image Operations lindscog 1986 1248
Kung. Why systolic architectures?. Computer, vol.15, no.1, 37-46.
Lenders, P., Schroder, H.. A programmable systolic device for image processing based on mathematical morphology. Parallel computing, vol.13, no.3, 337-344.
Systolic Array Processors frison 1989 145
Systolic Array Processors kean 1989 310
Proc of CAMP Architecture of Warp annaratone 1987 264
Systolic Algorithms and Architectures quinton 1991
※ AI-Helper는 부적절한 답변을 할 수 있습니다.